From 0c93a121c109c3e167d80173dbfe8c2e355b30ef Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 10 Apr 2018 21:24:49 -0700
Subject: Fix bug in Constant Propagation for registers propped to zero (#787)

It wasn't properly padding the width of the constant zero.
Also add a test that shows the buggy behavior.---
 .../scala/firrtl/transforms/ConstantPropagation.scala |  3 ++-
 .../scala/firrtlTests/ConstantPropagationTests.scala  | 19 +++++++++++++++++++
 2 files changed, 21 insertions(+), 1 deletion(-)

(limited to 'src')

diff --git a/src/main/scala/firrtl/transforms/ConstantPropagation.scala b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
index 2def130c..c417357b 100644
--- a/src/main/scala/firrtl/transforms/ConstantPropagation.scala
+++ b/src/main/scala/firrtl/transforms/ConstantPropagation.scala
@@ -379,7 +379,8 @@ class ConstantPropagation extends Transform {
           case Mux(_, tval: Literal, fval: WRef, _) if weq(lref, fval) =>
             nodeMap(lname) = constPropExpression(nodeMap, instMap, constSubOutputs)(pad(tval, ltpe))
           case WRef(`lname`, _,_,_) => // If a register is connected to itself, propagate zero
-            nodeMap(lname) = passes.RemoveValidIf.getGroundZero(ltpe)
+            val zero = passes.RemoveValidIf.getGroundZero(ltpe)
+            nodeMap(lname) = constPropExpression(nodeMap, instMap, constSubOutputs)(pad(zero, ltpe))
           case _ =>
         }
         // Mark instance inputs connected to a constant
diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index ca7daa17..c798ba37 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -836,6 +836,25 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
     execute(input, check, Seq.empty)
   }
 
+  it should "pad zero when constant propping a register replaced with zero" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output z : UInt<16>
+          |    reg r : UInt<8>, clock
+          |    r <= or(r, UInt(0))
+          |    node n = UInt("hab")
+          |    z <= cat(n, r)""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output z : UInt<16>
+          |    z <= UInt<16>("hab00")""".stripMargin
+    execute(input, check, Seq.empty)
+  }
+
   it should "pad constant connections to outputs when propagating" in {
       val input =
         """circuit Top :
-- 
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