From 06f57fefe8258c7d8149156db7ca01a66f207a5d Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 4 Jun 2015 14:56:18 -0700
Subject: Fixed fir files so they correctly compile to verilog! Front-end needs
 to generate as-SInt instead of convert, always. Added fast build to Makefile

---
 src/main/stanza/custom-compiler.stanza | 2 +-
 src/main/stanza/flo.stanza             | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'src')

diff --git a/src/main/stanza/custom-compiler.stanza b/src/main/stanza/custom-compiler.stanza
index aa21504b..773b63ca 100644
--- a/src/main/stanza/custom-compiler.stanza
+++ b/src/main/stanza/custom-compiler.stanza
@@ -32,7 +32,7 @@ public defmethod passes (c:InstrumentedVerilog) -> List<Pass> :
       SplitExp()
       ToRealIR()
       SpecialRename(`#,`_)
-      CheckHighForm(`_)
+      CheckHighForm(expand-delin)
       CheckLowForm()
       Verilog(file(c))
    ]
diff --git a/src/main/stanza/flo.stanza b/src/main/stanza/flo.stanza
index 22b0c978..fd000e20 100644
--- a/src/main/stanza/flo.stanza
+++ b/src/main/stanza/flo.stanza
@@ -89,7 +89,7 @@ public defn pad-widths (c:Circuit) -> Circuit :
    Circuit{info(c),_,main(c)} $
       for m in modules(c) map :
          match(m) :
-            (m:ExModule) : error("Cannot use flo backend with external modules")
+            (m:ExModule) : m
             (m:InModule) : InModule(info(m),name(m),ports(m),pad-widths-s(body(m)))
 
 ;============= Flo Backend ================
-- 
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