From 01b10725163c5bbe239c11f14b6136c737160d34 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Wed, 16 Oct 2019 01:33:30 -0700
Subject: Add test for #1179: comb-loops from VerilogMemDelays

---
 src/test/scala/firrtlTests/MemEnFeedbackSpec.scala | 41 ++++++++++++++++++++++
 1 file changed, 41 insertions(+)
 create mode 100644 src/test/scala/firrtlTests/MemEnFeedbackSpec.scala

(limited to 'src')

diff --git a/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala b/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala
new file mode 100644
index 00000000..d94d199a
--- /dev/null
+++ b/src/test/scala/firrtlTests/MemEnFeedbackSpec.scala
@@ -0,0 +1,41 @@
+// See LICENSE for license details.
+
+package firrtlTests
+
+import firrtl._
+
+// Tests long-standing bug from #1179, VerilogMemDelays producing combinational loops in corner case
+abstract class MemEnFeedbackSpec extends FirrtlFlatSpec {
+  val ruw: String
+  def input: String =
+    s"""circuit loop :
+       |  module loop :
+       |    input clk : Clock
+       |    input raddr : UInt<5>
+       |    mem m :
+       |      data-type => UInt<1>
+       |      depth => 32
+       |      reader => r
+       |      read-latency => 1
+       |      write-latency => 1
+       |      read-under-write => ${ruw}
+       |    m.r.clk <= clk
+       |    m.r.addr <= raddr
+       |    m.r.en <= m.r.data
+       |""".stripMargin
+  def compileInput(): Unit = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
+}
+
+class WriteFirstMemEnFeedbackSpec extends MemEnFeedbackSpec {
+  val ruw = "new"
+  "A write-first sync-read mem with feedback from data to enable" should "compile without errors" in {
+    compileInput()
+  }
+}
+
+class ReadFirstMemEnFeedbackSpec extends MemEnFeedbackSpec {
+  val ruw = "old"
+  "A read-first sync-read mem with feedback from data to enable" should "compile without errors" in {
+    compileInput()
+  }
+}
-- 
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