From fd8feb55cfa55e2c270d11c1a6ae60ba1950be59 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 28 Mar 2018 10:48:54 -0700
Subject: Replace unconnected registers with 0 in Constant Propagation (#776)

Moved from RemoveValidIf

Also Make RemoveValidIf.getGroundZero public and support Fixed
---
 .../firrtlTests/ConstantPropagationTests.scala     | 40 ++++++++++++++++++++++
 1 file changed, 40 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index 079b4823..ca7daa17 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -971,4 +971,44 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
           |    z <= mux(c, a, b)""".stripMargin
     execute(input, check, Seq.empty)
   }
+
+  "Registers connected only to themselves" should "be replaced with zero" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output a : UInt<8>
+          |    reg ra : UInt<8>, clock
+          |    ra <= ra
+          |    a <= ra
+          |""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output a : UInt<8>
+          |    a <= UInt<8>(0)
+          |""".stripMargin
+    execute(input, check, Seq.empty)
+  }
+
+  "Registers connected only to themselves from constant propagation" should "be replaced with zero" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output a : UInt<8>
+          |    reg ra : UInt<8>, clock
+          |    ra <= or(ra, UInt(0))
+          |    a <= ra
+          |""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    output a : UInt<8>
+          |    a <= UInt<8>(0)
+          |""".stripMargin
+    execute(input, check, Seq.empty)
+  }
 }
-- 
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