From fd5d4422df395064c87ec415a27a03d5a052088b Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 1 Feb 2021 14:03:43 -0500 Subject: Deprecate ToWorkingIR (#2028) * Deprecate firrtl.passes.ToWorkingIR Deprecate ToWorkingIR as it is now an identity transform. Signed-off-by: Schuyler Eldridge * Deprecate firrtl.stage.Forms.WorkingIR Signed-off-by: Schuyler Eldridge * Switch from Forms.WorkingIR to Forms.MinimalHighForm Signed-off-by: Schuyler Eldridge Co-authored-by: Jack Koenig Co-authored-by: mergify[bot] <37929162+mergify[bot]@users.noreply.github.com>--- src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index 54f0af8e..bdc72e7b 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -155,7 +155,10 @@ class LoweringCompilersSpec extends AnyFlatSpec with Matchers { it should "replicate the old order" in { val tm = new TransformManager(Forms.WorkingIR, Forms.MinimalHighForm) - compare(legacyTransforms(new firrtl.IRToWorkingIR), tm) + val patches = Seq( + Del(1) + ) + compare(legacyTransforms(new firrtl.IRToWorkingIR), tm, patches) } behavior.of("ResolveAndCheck") -- cgit v1.2.3