From f93dc6831e282338bcda1db04dbf272a36b4a895 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Sat, 9 Apr 2016 18:29:59 -0700
Subject: Adds check for type of DefRegister initialization

Fixes #89
---
 src/test/scala/firrtlTests/UnitTests.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index eda5d5d2..64f71180 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -27,4 +27,26 @@ class UnitTests extends FlatSpec with Matchers {
       }
     }
   }
+
+  "Initializing a register with a different type" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes)
+    val input =
+     """circuit Unit :
+       |  module Unit :
+       |    input clk : Clock
+       |    input reset : UInt<1>
+       |    wire x : { valid : UInt<1> }
+       |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
+       |      reset => (reset, x)""".stripMargin
+    intercept[PassExceptions] {
+      passes.foldLeft(Parser.parse("",input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
 }
-- 
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