From f7b4aa8a3a759c94e0de8e1aeeacc69d3d702945 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Thu, 7 Apr 2022 17:07:48 -0700
Subject: Make MemConf's MemPort serialization deterministic (#2508)

Problem: MemConf serialization of MemPorts was not deterministic
and the ordering seems to have changed as we move projects to 2.13
Downstream project can be adversely affected by changes in ordering
This changes specifies as specific ordering that should be compatible with
the historical one.---
 src/test/scala/firrtlTests/ReplSeqMemTests.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
index d9dc2e57..e8d72043 100644
--- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala
+++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala
@@ -693,4 +693,16 @@ circuit Top :
          |""".stripMargin
     compileAndEmit(CircuitState(parse(input), ChirrtlForm))
   }
+
+  "MemPorts" should "serialize in a deterministic order regardless" in {
+    def compare(seq1: Seq[MemPort]) {
+      val m1 = MemConf("memconf", 8, 16, seq1.map(s => s -> 1).toMap, None)
+      val m2 = MemConf("memconf", 8, 16, seq1.reverse.map(s => s -> 1).toMap, None)
+      m1.toString should be(m2.toString)
+    }
+
+    compare(Seq(ReadPort, WritePort))
+    compare(Seq(MaskedWritePort, ReadWritePort))
+    compare(Seq(MaskedReadWritePort, WritePort, ReadWritePort))
+  }
 }
-- 
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