From b0623fe1856caeba11cda1ccaf68f094489169a7 Mon Sep 17 00:00:00 2001
From: grebe
Date: Thu, 19 Jan 2017 09:12:13 -0800
Subject: Verilog rem fix (#404)

* Add pass that fixes up widths with modulus operator for verilog

* Add basic test for Verilog emission of Rem

* Oops, left in some printlns.
---
 .../scala/firrtlTests/VerilogEmitterTests.scala     | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
index 39592269..41fd6e41 100644
--- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala
+++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala
@@ -74,4 +74,25 @@ class DoPrimVerilog extends FirrtlFlatSpec {
         |""".stripMargin.split("\n") map normalized
     executeTest(input, check, compiler)
   }
+  "Rem" should "emit correctly" in {
+    val compiler = new VerilogCompiler
+    val input =
+      """circuit Test :
+        |  module Test :
+        |    input in : UInt<8>
+        |    output out : UInt<1>
+        |    out <= rem(in, UInt<1>("h1"))
+        |""".stripMargin
+    val check =
+      """module Test(
+        |  input  [7:0] in, 
+        |  output  out 
+        |);
+        |  wire [7:0] _GEN_0;
+        |  assign out = _GEN_0[0];
+        |  assign _GEN_0 = in % 8'h1;
+        |endmodule
+        |""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler)
+  }
 }
-- 
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