From e0e685685074c493ea077bccacbbec9b5b2d33ee Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 23 Jun 2020 20:20:47 -0700
Subject: Don't Dedup modules if it would change semantics (#1713)

If a module has ports of type Bundle that are used in aggregate
connections in parent modules, Dedup cannot change the names of the
fields of the Bundle or it would change the semantics of the connection.
Dedup now detects this case and refrains from agnostifying the ports of
such modules to prevent this issue.---
 .../scala/firrtlTests/transforms/DedupTests.scala  | 67 ++++++++++++++++++++--
 1 file changed, 63 insertions(+), 4 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index bb12c759..5776db31 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -253,6 +253,61 @@ class DedupModuleTests extends HighTransformSpec {
      val diff_params = mkfir(("BB", "BB"), ("0", "1"))
      execute(diff_params, diff_params, Seq.empty)
   }
+
+  "Modules with aggregate ports that are bulk connected" should "NOT dedup if their port names differ" in {
+    val input =
+      """
+        |circuit FooAndBarModule :
+        |  module FooModule :
+        |    output io : {flip foo : UInt<1>, fuzz : UInt<1>}
+        |    io.fuzz <= io.foo
+        |  module BarModule :
+        |    output io : {flip bar : UInt<1>, buzz : UInt<1>}
+        |    io.buzz <= io.bar
+        |  module FooAndBarModule :
+        |    output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}}
+        |    inst foo of FooModule
+        |    inst bar of BarModule
+        |    io.foo <- foo.io
+        |    io.bar <- bar.io
+        |""".stripMargin
+    val check = input
+    execute(input, check, Seq.empty)
+  }
+
+  "Modules with aggregate ports that are bulk connected" should "dedup if their port names are the same" in {
+    val input =
+      """
+        |circuit FooAndBarModule :
+        |  module FooModule :
+        |    output io : {flip foo : UInt<1>, fuzz : UInt<1>}
+        |    io.fuzz <= io.foo
+        |  module BarModule :
+        |    output io : {flip foo : UInt<1>, fuzz : UInt<1>}
+        |    io.fuzz <= io.foo
+        |  module FooAndBarModule :
+        |    output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}}
+        |    inst foo of FooModule
+        |    inst bar of BarModule
+        |    io.foo <- foo.io
+        |    io.bar <- bar.io
+        |""".stripMargin
+    val check =
+      """
+        |circuit FooAndBarModule :
+        |  module FooModule :
+        |    output io : {flip foo : UInt<1>, fuzz : UInt<1>}
+        |    io.fuzz <= io.foo
+        |  module FooAndBarModule :
+        |    output io : {foo : {flip foo : UInt<1>, fuzz : UInt<1>}, bar : {flip bar : UInt<1>, buzz : UInt<1>}}
+        |    inst foo of FooModule
+        |    inst bar of FooModule
+        |    io.foo <- foo.io
+        |    io.bar <- bar.io
+        |""".stripMargin
+    execute(input, check, Seq.empty)
+  }
+
   "The module A and B" should "be deduped with the first module in order" in {
     val input =
       """circuit Top :
@@ -772,11 +827,15 @@ class DedupModuleTests extends HighTransformSpec {
       |    output oa: {z: {y: {x: UInt<1>}}, a: UInt<1>}
       |    output ob: {a: {b: {c: UInt<1>}}, z: UInt<1>}
       |    inst a of a
-      |    a.i <= ia
-      |    oa <= a.o
+      |    a.i.z.y.x <= ia.z.y.x
+      |    a.i.a <= ia.a
+      |    oa.z.y.x <= a.o.z.y.x
+      |    oa.a <= a.o.a
       |    inst b of b
-      |    b.q <= ib
-      |    ob <= b.r
+      |    b.q.a.b.c <= ib.a.b.c
+      |    b.q.z <= ib.z
+      |    ob.a.b.c <= b.r.a.b.c
+      |    ob.z <= b.r.z
       |  module a:
       |    input i: {z: {y: {x: UInt<1>}}, a: UInt<1>}
       |    output o: {z: {y: {x: UInt<1>}}, a: UInt<1>}
-- 
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