From dd72b24dde5b28aef4a3728fdb770e26f5dbc54d Mon Sep 17 00:00:00 2001 From: Adam Izraelevitz Date: Fri, 6 Mar 2020 18:03:55 -0800 Subject: Add firrtl-json serializers (#1430) * Add firrtl-json serializers * Added support for ports, info. Added docs and tests--- .../annotationTests/JsonProtocolSpec.scala | 42 ++++++++++++++++++++++ 1 file changed, 42 insertions(+) create mode 100644 src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala b/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala new file mode 100644 index 00000000..2dce89db --- /dev/null +++ b/src/test/scala/firrtlTests/annotationTests/JsonProtocolSpec.scala @@ -0,0 +1,42 @@ +// See LICENSE for license details. + +package firrtlTests.annotationTests + +import firrtl.Parser +import firrtl.annotations.{Annotation, JsonProtocol, NoTargetAnnotation} +import firrtl.ir._ +import org.scalatest.{FlatSpec, Matchers, PropSpec} + +case class AnAnnotation( + info: Info, + cir: Circuit, + mod: DefModule, + port: Port, + statement: Statement, + expr: Expression, + tpe: Type +) extends NoTargetAnnotation + +class JsonProtocolSpec extends FlatSpec with Matchers { + "JsonProtocol" should "serialize and deserialize FIRRTL types" in { + + val circuit = + """circuit Top: @[FPU.scala 509:25] + | module Top: + | input x: UInt + | output y: UInt + | y <= add(x, x) + |""".stripMargin + val cir = Parser.parse(circuit) + val mod = cir.modules.head + val port = mod.ports.head + val stmt = mod.asInstanceOf[Module].body + val expr = stmt.asInstanceOf[Block].stmts.head.asInstanceOf[Connect].expr + val tpe = port.tpe + val inputAnnos = Seq(AnAnnotation(cir.info, cir, mod, port, stmt, expr, tpe)) + val annosString = JsonProtocol.serialize(inputAnnos) + val outputAnnos = JsonProtocol.deserialize(annosString) + inputAnnos should be (outputAnnos) + } + +} -- cgit v1.2.3