From 12faf3c058675951b8d3434e2965e121900c8e6b Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Mon, 4 Oct 2021 22:49:23 -0400 Subject: Add test of #2379 issue, NFC Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/ReplSeqMemTests.scala | 21 +++++++++++++++++++++ 1 file changed, 21 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/ReplSeqMemTests.scala b/src/test/scala/firrtlTests/ReplSeqMemTests.scala index 924c767f..d9dc2e57 100644 --- a/src/test/scala/firrtlTests/ReplSeqMemTests.scala +++ b/src/test/scala/firrtlTests/ReplSeqMemTests.scala @@ -672,4 +672,25 @@ circuit Top : ) resAnnos should be(expected) } + + "ReplSeqMem" should "not crash if there are aggregate registers in the design that require padding (see #2379)" in { + + val input = + """|circuit Foo: + | module Foo: + | input clock: Clock + | input reset: UInt<1> + | input a: UInt<1>[1] + | output b: UInt<2>[1] + | + | wire init: UInt<1>[1] + | init <= a + | + | reg r : UInt<2>[1], clock with : + | reset => (reset, init) + | + | b <= r + |""".stripMargin + compileAndEmit(CircuitState(parse(input), ChirrtlForm)) + } } -- cgit v1.2.3