From 334c9bbe5061a3bcb72df971ec555de7df0ba36c Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 25 Jan 2019 14:04:16 -0500 Subject: Add "mverilog" Compiler Option, Compiler Fixes This adds "mverilog" to the "--compiler" command line option. This will run the MinimumVerilogCompiler. This additionally fixes the MinimumVerilogCompiler such that DeadCodeElimination will not be run (it's not supposed to be). This is done by adding a MinimumVerilogEmitter, subclassing VerilogVerilog, that strips the DeadCodeElimination step from its parent. Additionally, BlackBoxSourceHelper is removed from the MinimumVerilogCompiler since this will be run by the VerilogEmitter already. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/CompilerTests.scala | 29 ++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index 348ed300..ff7d2cb8 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -13,6 +13,7 @@ import firrtl.{ Compiler, HighFirrtlCompiler, MiddleFirrtlCompiler, + MinimumVerilogCompiler, LowFirrtlCompiler, Parser, VerilogCompiler @@ -153,3 +154,31 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers { getOutput should be (check) } } + +class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers { + val input = """|circuit Top: + | module Top: + | output b: UInt<1>[2] + | node c = UInt<1>("h0") + | node d = UInt<1>("h0") + | b[0] <= UInt<1>("h0") + | b[1] <= c + |""".stripMargin + val check = """|module Top( + | output b_0, + | output b_1 + |); + | wire c; + | wire d; + | assign c = 1'h0; + | assign d = 1'h0; + | assign b_0 = 1'h0; + | assign b_1 = c; + |endmodule + |""".stripMargin + def compiler = new MinimumVerilogCompiler() + + "A circuit's minimum Verilog output" should "not have constants propagated or dead code eliminated" in { + getOutput should be (check) + } +} -- cgit v1.2.3 From 6ef7ad148ff491c06d417d417e2134da7ff49ef7 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 25 Jan 2019 14:53:13 -0500 Subject: Add "mverilog" and "sverilog" DriverSpec tests This adds runs of the minimum Verilog compiler and SystemVerilog compiler in DriverSpec. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/DriverSpec.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index 545bf09a..ae1e08e7 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -371,7 +371,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> "./Top.lo.fir", "high" -> "./Top.hi.fir", "middle" -> "./Top.mid.fir", - "verilog" -> "./Top.v" + "verilog" -> "./Top.v", + "mverilog" -> "./Top.v", + "sverilog" -> "./Top.sv" ).foreach { case (compilerName, expectedOutputFileName) => val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { commonOptions = CommonOptions(topName = "Top") @@ -391,7 +393,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> Seq("./Top.lo.fir", "./Child.lo.fir"), "high" -> Seq("./Top.hi.fir", "./Child.hi.fir"), "middle" -> Seq("./Top.mid.fir", "./Child.mid.fir"), - "verilog" -> Seq("./Top.v", "./Child.v") + "verilog" -> Seq("./Top.v", "./Child.v"), + "mverilog" -> Seq("./Top.v", "./Child.v"), + "sverilog" -> Seq("./Top.sv", "./Child.sv") ).foreach { case (compilerName, expectedOutputFileNames) => println(s"$compilerName -> $expectedOutputFileNames") val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { -- cgit v1.2.3 From a77122b4bb8756636c169473af3dc367b14698ef Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 5 Feb 2019 11:23:19 -0500 Subject: Add RemoveValidIf to -X mverilog This adds the RemoveValidIf Pass to the MinimumLowFirrtlOptimization Transform. A test case is included to verify that `is invalid` is properly converted to a connection to zero. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/CompilerTests.scala | 15 ++++++--------- 1 file changed, 6 insertions(+), 9 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index ff7d2cb8..df83dd38 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -159,21 +159,18 @@ class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers { val input = """|circuit Top: | module Top: | output b: UInt<1>[2] - | node c = UInt<1>("h0") - | node d = UInt<1>("h0") - | b[0] <= UInt<1>("h0") - | b[1] <= c + | node c = UInt<1>("h1") + | b[0] <= c + | b[1] is invalid |""".stripMargin val check = """|module Top( | output b_0, | output b_1 |); | wire c; - | wire d; - | assign c = 1'h0; - | assign d = 1'h0; - | assign b_0 = 1'h0; - | assign b_1 = c; + | assign c = 1'h1; + | assign b_0 = c; + | assign b_1 = 1'h0; |endmodule |""".stripMargin def compiler = new MinimumVerilogCompiler() -- cgit v1.2.3 From 0a88492bfbbfe7e446b74776ec59cab69e73585b Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 5 Feb 2019 14:03:08 -0500 Subject: Do Shr constant propagation in Legalize This uses the foldShiftRight method of the ConstantPropagation Transform when legalizing Shr PrimOps. This has the effect of removing literals with bit extracts from the MinimumVerilogCompiler. This makes the formerly private foldShiftRight method of a public method of the ConstantPropagation companion object. Tests in the MimimumVerilogCompilerSpec are updated to check that Shr is handled as intended. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/CompilerTests.scala | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/CompilerTests.scala b/src/test/scala/firrtlTests/CompilerTests.scala index df83dd38..dc70847a 100644 --- a/src/test/scala/firrtlTests/CompilerTests.scala +++ b/src/test/scala/firrtlTests/CompilerTests.scala @@ -158,19 +158,25 @@ class VerilogCompilerSpec extends CompilerSpec with Matchers { class MinimumVerilogCompilerSpec extends CompilerSpec with Matchers { val input = """|circuit Top: | module Top: - | output b: UInt<1>[2] - | node c = UInt<1>("h1") - | b[0] <= c - | b[1] is invalid + | output b: UInt<1>[3] + | node c = bits(UInt<3>("h7"), 2, 2) + | node d = shr(UInt<3>("h7"), 2) + | b[0] is invalid + | b[1] <= c + | b[2] <= d |""".stripMargin val check = """|module Top( | output b_0, - | output b_1 + | output b_1, + | output b_2 |); | wire c; + | wire d; | assign c = 1'h1; - | assign b_0 = c; - | assign b_1 = 1'h0; + | assign d = 1'h1; + | assign b_0 = 1'h0; + | assign b_1 = c; + | assign b_2 = d; |endmodule |""".stripMargin def compiler = new MinimumVerilogCompiler() -- cgit v1.2.3