From a5c3589e7bd680bcf7db25e8fd3282d73c5e24ae Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Mon, 5 Nov 2018 12:10:21 -0500
Subject: Add prettyPrint method to Target

This adds a pretty printer for firrtl.annotation.Target and associated
tests. This uses a tree-like output where the following target
~Circuit|Module/foo:Foo>ref.field[0] will serialize to:

  circuit Circuit:
  └── module Module:
      └── foo of Foo:
          └── ref.field[0]

This enables better error messages and a human readable syntax better than
the existing serialize method (and avoiding the need for users to
understand the Target serialization syntax), but that is not intended to
be deserialized nor space efficient.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 .../firrtlTests/annotationTests/TargetSpec.scala   | 28 +++++++++++++++++++++-
 1 file changed, 27 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
index 4ae4e036..da154b6a 100644
--- a/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
+++ b/src/test/scala/firrtlTests/annotationTests/TargetSpec.scala
@@ -55,5 +55,31 @@ class TargetSpec extends FirrtlPropSpec {
       assert(Target.deserialize(t.serialize) == t, s"$t does not properly serialize/deserialize")
     }
   }
+  property("Pretty Printer should work") {
+    val circuit = CircuitTarget("A")
+    val top = circuit.module("B")
+    val targets = Seq(
+      (circuit, "circuit A:"),
+      (top,
+       """|circuit A:
+          |└── module B:""".stripMargin),
+      (top.instOf("c", "C"),
+       """|circuit A:
+          |└── module B:
+          |    └── inst c of C:""".stripMargin),
+      (top.ref("r"),
+       """|circuit A:
+          |└── module B:
+          |    └── r""".stripMargin),
+      (top.ref("r").index(1).field("hi").clock,
+       """|circuit A:
+          |└── module B:
+          |    └── r[1].hi@clock""".stripMargin),
+      (GenericTarget(None, None, Vector(Ref("r"))),
+       """|circuit ???:
+          |└── module ???:
+          |    └── r""".stripMargin)
+    )
+    targets.foreach { case (t, str) => assert(t.prettyPrint() == str, s"$t didn't properly prettyPrint") }
+  }
 }
-
-- 
cgit v1.2.3


From 2fdc984223393ee4996f7f7fde8d6b12c9fe36c3 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Thu, 25 Oct 2018 16:40:59 -0400
Subject: Better error message for UninferredWidth exception

This changes the CheckTypes.UniferredWidth exception to include the pretty
printed Target that was uninferred and suggests to the user that they may
have forgotten to assign to it. This changes the CheckTypes pass to
communicate the necessary Target information during AST traversal such
that when an uninferred width is found, the Target is known and available.

This also adds one test checking the message of the UniferredWidth
exception.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
---
 src/test/scala/firrtlTests/WidthSpec.scala | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index ab8cb7ac..058cc1fa 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -156,4 +156,29 @@ class WidthSpec extends FirrtlFlatSpec {
       executeTest(input, check, passes)
     }
   }
+
+  behavior of "CheckWidths.UniferredWidth"
+
+  it should "provide a good error message with a full target if a user forgets an assign" in {
+    val passes = Seq(
+      ToWorkingIR,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      ResolveGenders,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """|circuit Foo :
+         |  module Foo :
+         |    input clock : Clock
+         |    inst bar of Bar
+         |  module Bar :
+         |    wire a: { b : UInt<1>, c : { d : UInt<1>, e : UInt } }
+         |""".stripMargin
+    val msg = intercept[CheckWidths.UninferredWidth] { executeTest(input, Nil, passes) }
+      .getMessage should include ("""|    circuit Foo:
+                                     |    └── module Bar:
+                                     |        └── a.c.e""".stripMargin)
+  }
 }
-- 
cgit v1.2.3