From cc80c631e2a6a259f33d1d583107d5add05aaf12 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Thu, 26 Aug 2021 13:40:59 -0400 Subject: Fix dshl zero-width shift behavior (#2339) * Fix dshl zero-width shift behavior Add a special case for dshl handling in the ZeroWidths pass. If one expression is shifted by a second, zero-width expression, just return the first expression. This prevents a bug where the width will incorrectly expand due to zero-widths introducing a 1-bit zero expression. Signed-off-by: Schuyler Eldridge * fixup! Fix dshl zero-width shift behavior--- src/test/scala/firrtlTests/ZeroWidthTests.scala | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala index 654c6f42..4e22ff51 100644 --- a/src/test/scala/firrtlTests/ZeroWidthTests.scala +++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala @@ -238,6 +238,23 @@ class ZeroWidthTests extends FirrtlFlatSpec { (parse(exec(input))) should be(parse(check)) } + "dshl with zero-width" should "canonicalize to the un-shifted expression" in { + val input = + """circuit Top : + | module Top : + | input x : UInt<0> + | input y : SInt<1> + | output z : SInt<1> + | z <= dshl(y, x)""".stripMargin + val check = + """circuit Top : + | module Top : + | input y : SInt<1> + | output z : SInt<1> + | z <= y""".stripMargin + (parse(exec(input))) should be(parse(check)) + } + "Memories with zero-width data-type" should "be fully removed" in { val input = """circuit Foo: -- cgit v1.2.3