From cbfb32dc90f25c814898add3eff9b332b6021e5b Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Thu, 25 Jun 2020 15:13:07 -0700
Subject: Enable ConvertAsserts in default Verilog compiler

---
 src/test/scala/firrtlTests/CustomTransformSpec.scala   | 4 +++-
 src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 2 ++
 2 files changed, 5 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CustomTransformSpec.scala b/src/test/scala/firrtlTests/CustomTransformSpec.scala
index 677aa6ff..7a683ea9 100644
--- a/src/test/scala/firrtlTests/CustomTransformSpec.scala
+++ b/src/test/scala/firrtlTests/CustomTransformSpec.scala
@@ -10,7 +10,7 @@ import firrtl.stage.{FirrtlSourceAnnotation, FirrtlStage, Forms, RunFirrtlTransf
 import firrtl.options.Dependency
 import firrtl.transforms.{IdentityTransform, LegalizeAndReductionsTransform}
 import firrtl.testutils._
-import firrtl.transforms.formal.RemoveVerificationStatements
+import firrtl.transforms.formal.{RemoveVerificationStatements, ConvertAsserts}
 
 import scala.reflect.runtime
 
@@ -174,9 +174,11 @@ class CustomTransformSpec extends FirrtlFlatSpec {
 
     Seq( (Seq(Dependency[LowFirrtlEmitter]),             Seq(low.last)      ),
          (Seq(Dependency[LegalizeAndReductionsTransform],
+           Dependency(ConvertAsserts),
            Dependency[RemoveVerificationStatements],
            Dependency[MinimumVerilogEmitter]),           Seq(lowMinOpt.last)),
          (Seq(Dependency[LegalizeAndReductionsTransform],
+           Dependency(ConvertAsserts),
            Dependency[RemoveVerificationStatements],
            Dependency[VerilogEmitter]),                  Seq(lowOpt.last)    ),
          (Seq(Dependency[LegalizeAndReductionsTransform],
diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
index 75f2ea02..82750fdf 100644
--- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
+++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala
@@ -354,6 +354,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
     val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow])))
     val patches = Seq(
       Add(63, Seq(
+        Dependency(firrtl.transforms.formal.ConvertAsserts),
         Dependency[firrtl.transforms.formal.RemoveVerificationStatements],
         Dependency[firrtl.transforms.LegalizeAndReductionsTransform]))
     )
@@ -367,6 +368,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers {
     val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow])))
     val patches = Seq(
       Add(70, Seq(
+        Dependency(firrtl.transforms.formal.ConvertAsserts),
         Dependency[firrtl.transforms.formal.RemoveVerificationStatements],
         Dependency[firrtl.transforms.LegalizeAndReductionsTransform]))
     )
-- 
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