From c7bbb75b8b293d639848abaa9f68121f80947f42 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 11 Nov 2020 16:07:54 -0800
Subject: Fix RemoveWires handling of invalidated non-UInt wires (#1949)

It would replace them with a validif node with a UIntLiteral which can
lead to type errors.---
 src/test/scala/firrtlTests/RemoveWiresSpec.scala | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index 48eaaa65..58d42710 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -6,6 +6,7 @@ import firrtl._
 import firrtl.ir._
 import firrtl.Mappers._
 import firrtl.testutils._
+import FirrtlCheckers._
 
 import collection.mutable
 
@@ -187,4 +188,17 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     firrtl.passes.CheckHighForm.execute(result)
   }
 
+  it should "give nodes made from invalid wires the correct type" in {
+    val result = compileBody(
+      s"""|input  a   : SInt<4>
+          |input  sel : UInt<1>
+          |output z   : SInt<4>
+          |wire w : SInt<4>
+          |w is invalid
+          |z <= mux(sel, a, w)
+          |""".stripMargin
+    )
+    result should containLine("""node w = validif(UInt<1>("h0"), SInt<4>("h0"))""")
+  }
+
 }
-- 
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