From c6c509d623e5e64e021fa311018b8ace2f3f8969 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Wed, 7 Aug 2019 16:33:45 -0700
Subject: Check mems for legal latencies; ban zero write latency. (#1147)

* Check mems for legal latencies; ban zero write latency.

* Trigger
---
 src/test/scala/firrtlTests/CheckSpec.scala | 19 +++++++++++++++++++
 1 file changed, 19 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 93bc2cab..54dc60ab 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -41,6 +41,25 @@ class CheckSpec extends FlatSpec with Matchers {
     }
   }
 
+  "Memories with zero write latency" should "throw an exception" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    mem m :
+        |      data-type => UInt<32>
+        |      depth => 32
+        |      read-latency => 0
+        |      write-latency => 0""".stripMargin
+    intercept[CheckHighForm.IllegalMemLatencyException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
   "Registers with flip in the type" should "throw an exception" in {
     val input =
       """circuit Unit :
-- 
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