From bb389aa69f0b6a99c3daecbf02e4df1e303ec636 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Sun, 29 Jan 2017 14:05:13 -0800
Subject: Keep firrtl's simulation environment in sync with chisel's. (#425)

---
 src/test/resources/top.cpp | 8 ++++++++
 1 file changed, 8 insertions(+)

(limited to 'src/test')

diff --git a/src/test/resources/top.cpp b/src/test/resources/top.cpp
index 08ad42fa..ba27c917 100644
--- a/src/test/resources/top.cpp
+++ b/src/test/resources/top.cpp
@@ -7,6 +7,13 @@
 # include <verilated_vcd_c.h>	// Trace file format header
 #endif
 
+// Override Verilator definition so first $finish ends simulation
+// Note: VL_USER_FINISH needs to be defined when compiling Verilator code
+void vl_finish(const char* filename, int linenum, const char* hier) {
+  Verilated::flushCall();
+  exit(0);
+}
+
 using namespace std;
 
 //VGCDTester *top;
@@ -61,6 +68,7 @@ int main(int argc, char** argv) {
   if (main_time >= timeout) {
       cout << "Assertion failed! Simulation terminated by timeout at time " << main_time <<
               " (cycle " << main_time / 10 << ")"<< endl;
+      return -1;
   } else {
       cout << "Simulation completed at time " << main_time <<
               " (cycle " << main_time / 10 << ")"<< endl;
-- 
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