From b1709242b5c7b60e21308642947d292545eb2e37 Mon Sep 17 00:00:00 2001
From: grebe
Date: Mon, 21 May 2018 13:09:00 -0700
Subject: Fix more problems with zero width things. (#779)

This should close #757. It should also allow for stop() and printf()
to be used with zero-width fields.
---
 src/test/resources/features/ZeroWidthMem.fir    |  9 ++++++-
 src/test/scala/firrtlTests/ZeroWidthTests.scala | 36 +++++++++++++++++++++++++
 2 files changed, 44 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/resources/features/ZeroWidthMem.fir b/src/test/resources/features/ZeroWidthMem.fir
index c56f8390..a909b041 100644
--- a/src/test/resources/features/ZeroWidthMem.fir
+++ b/src/test/resources/features/ZeroWidthMem.fir
@@ -12,9 +12,13 @@ circuit ZeroWidthMem :
     infer mport ramin = ram[waddr], clock
     infer mport ramout = ram[raddr], clock
 
+    cmem totallyEmptyRam : UInt<0>[16]
+    infer mport emptyRamout = totallyEmptyRam[raddr], clock
+
     ramin.0 <= in.0
     ramin.1 <= in.1
-    out <= ramout
+    out.0   <= ramout.0
+    out.1   <= ramout.1
 
     wire foo : UInt<32>
     foo <= UInt<32>("hdeadbeef")
@@ -26,3 +30,6 @@ circuit ZeroWidthMem :
         printf(clock, UInt(1), "Assertion failed!\n")
         stop(clock, UInt(1), 1) ; Failure!
 
+    when neq(emptyRamout, UInt<1>("h0")) :
+      stop(clock, UInt(1), 1) ; Failure! empty mem should be zero
+
diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index 50385a80..6443e131 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -176,6 +176,42 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    node a = cat(x, z)""".stripMargin
       (parse(exec(input)).serialize) should be (parse(check).serialize)
   }
+  "Stop with type <0>" should "be replaced with UInt(0)" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    input z: UInt<1>
+        |    stop(clk, y, 1)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input z: UInt<1>
+        |    stop(clk, UInt(0), 1)""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  "Print with type <0>" should "be replaced with UInt(0)" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    input z: UInt<1>
+        |    printf(clk, UInt(1), "%d %d %d\n", x, y, z)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input clk: Clock
+        |    input x: UInt<1>
+        |    input z: UInt<1>
+        |    printf(clk, UInt(1), "%d %d %d\n", x, UInt(0), z)""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
 }
 
 class ZeroWidthVerilog extends FirrtlFlatSpec {
-- 
cgit v1.2.3