From afde65773fc7b19dd99e0c65f718a96d0466541b Mon Sep 17 00:00:00 2001
From: azidar
Date: Wed, 18 Feb 2015 08:24:20 -0800
Subject: Reimplemented to-working-ir. Changed Command to Stmt. Modified
 printing of IR to match parser.

---
 src/test/firrtl/firrtl-test.txt | 44 +++++++++++++----------------------------
 1 file changed, 14 insertions(+), 30 deletions(-)

(limited to 'src/test')

diff --git a/src/test/firrtl/firrtl-test.txt b/src/test/firrtl/firrtl-test.txt
index 7d8e66d2..1f3db390 100644
--- a/src/test/firrtl/firrtl-test.txt
+++ b/src/test/firrtl/firrtl-test.txt
@@ -1,22 +1,19 @@
 circuit top :
    module subtracter :
-      input x:UInt
-      input y:UInt
-      output z:UInt
+      input x : UInt
+      input y : UInt
+      output z : UInt
       z := sub-mod(x, y)
-
    module gcd :
-      input a: UInt(16)
-      input b: UInt(16)
-      input e: UInt(1)
-      output z: UInt(16)
-      output v: UInt(1)
-
-      reg x: UInt
-      reg y: UInt
+      input a : UInt(16)
+      input b : UInt(16)
+      input e : UInt(1)
+      output z : UInt(16)
+      output v : UInt(1)
+      reg x : UInt
+      reg y : UInt
       x.init := UInt(0)
       y.init := UInt(42)
-
       when greater(x, y) :
          inst s of subtracter
          s.x := x
@@ -27,30 +24,17 @@ circuit top :
          s2.x := x
          s2.y := y
          y := s2.z
-      
       when e :
          x := a
          y := b
-
       v := equal(v, UInt(0))
       z := x
-
-   module top :   
-      input a: UInt(16)
-      input b: UInt(16)
-      output z: UInt
-
+   module top :
+      input a : UInt(16)
+      input b : UInt(16)
+      output z : UInt
       inst i of gcd
       i.a := a
       i.b := b
       i.e := UInt(1)
       z := i.z
-
- 
-
-
-
-
-      
-
-
-- 
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