From ad36788b79f8b63be59d9612134889aef874c286 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 5 Dec 2016 09:29:40 -0800
Subject: Bugfix: expand whens not voiding memories (#380)

---
 src/test/scala/firrtlTests/ExpandWhensSpec.scala | 52 ++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 4 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index 6d1a74c0..a7824087 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -11,14 +11,17 @@ import firrtl.ir._
 import firrtl.Parser.IgnoreInfo
 
 class ExpandWhensSpec extends FirrtlFlatSpec {
-  private def executeTest(input: String, notExpected: String, passes: Seq[Pass]) = {
+  private def executeTest(input: String, check: String, passes: Seq[Pass], expected: Boolean) = {
     val c = passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
       (c: Circuit, p: Pass) => p.run(c)
     }
     val lines = c.serialize.split("\n") map normalized
+    println(c.serialize)
 
-    lines foreach { l =>
-      l.contains(notExpected) should be (false)
+    if(expected) {
+      c.serialize.contains(check) should be (true)
+    } else {
+      lines foreach { l => l.contains(check) should be (false) }
     }
   }
   "Expand Whens" should "not emit INVALID" in {
@@ -48,7 +51,48 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
      |      a is invalid
      |      a.b <= UInt<64>("h04000000000000000")""".stripMargin
     val check = "INVALID"
-    executeTest(input, check, passes)
+    executeTest(input, check, passes, false)
+  }
+  "Expand Whens" should "void unwritten memory fields" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      Uniquify,
+      ResolveKinds,
+      InferTypes,
+      ResolveGenders,
+      CheckGenders,
+      InferWidths,
+      CheckWidths,
+      PullMuxes,
+      ExpandConnects,
+      RemoveAccesses,
+      ExpandWhens)
+    val input =
+  """|circuit Tester : 
+     |  module Tester :
+     |    input clk : Clock
+     |    mem memory:
+     |      data-type => UInt<32>
+     |      depth => 32
+     |      reader => r0
+     |      writer => w0
+     |      read-latency => 0
+     |      write-latency => 1
+     |      read-under-write => undefined
+     |    memory.r0.addr <= UInt<1>(1)
+     |    memory.r0.en <= UInt<1>(1)
+     |    memory.r0.clk <= clk
+     |    memory.w0.addr <= UInt<1>(1)
+     |    memory.w0.data <= UInt<1>(1)
+     |    memory.w0.en <= UInt<1>(1)
+     |    memory.w0.clk <= clk
+     |    """.stripMargin
+    val check = "VOID"
+    executeTest(input, check, passes, true)
   }
 }
 
-- 
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