From a84956afa36dbe29e87dd6c2168848a426ec42d3 Mon Sep 17 00:00:00 2001
From: Andrey Ayupov
Date: Fri, 4 Aug 2017 11:02:41 -0700
Subject: bug fix for cases when we want to flatten a module in which a module
 is instantiated multiple times (#634)

---
 src/test/scala/firrtlTests/FlattenTests.scala | 41 ++++++++++++++++++++++++++-
 1 file changed, 40 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/FlattenTests.scala b/src/test/scala/firrtlTests/FlattenTests.scala
index f695cf4a..10988f8f 100644
--- a/src/test/scala/firrtlTests/FlattenTests.scala
+++ b/src/test/scala/firrtlTests/FlattenTests.scala
@@ -26,7 +26,6 @@ class FlattenTests extends LowTransformSpec {
     FlattenAnnotation(name)
   }
   
-  
   "The modules inside Top " should "be inlined" in {
      val input =
         """circuit Top :
@@ -56,6 +55,46 @@ class FlattenTests extends LowTransformSpec {
           |    b <= a""".stripMargin
      execute(input, check, Seq(flatten("Top")))
   }
+  
+  "Two instances of the same module inside Top " should "be inlined" in {
+     val input =
+        """circuit Top :
+          |  module Top :
+          |    input a : UInt<32>
+          |    output b : UInt<32>
+          |    inst i1 of Inline1
+          |    inst i2 of Inline1
+          |    wire tmp : UInt<32>
+          |    i1.a <= a
+          |    tmp <= i1.b
+          |    i2.a <= tmp
+          |    b <= i2.b
+          |  module Inline1 :
+          |    input a : UInt<32>
+          |    output b : UInt<32>
+          |    b <= a""".stripMargin
+     val check =
+        """circuit Top :
+          |  module Top :
+          |    input a : UInt<32>
+          |    output b : UInt<32>
+          |    wire i1$a : UInt<32>
+          |    wire i1$b : UInt<32>
+          |    i1$b <= i1$a
+          |    wire i2$a : UInt<32>
+          |    wire i2$b : UInt<32>
+          |    i2$b <= i2$a
+          |    wire tmp : UInt<32>
+          |    b <= i2$b
+          |    tmp <= i1$b
+          |    i1$a <= a
+          |    i2$a <= tmp
+          |  module Inline1 :
+          |    input a : UInt<32>
+          |    output b : UInt<32>
+          |    b <= a""".stripMargin
+     execute(input, check, Seq(flatten("Top")))
+  }
 
   "The module instance i in Top " should "be inlined" in {
      val input =
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