From a2ad26d6b907b251a916c23a3fe93e1d0067fb03 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 26 Sep 2016 16:12:00 -0700
Subject: Added max width check to dshl shift amount (#318)

Address #297---
 src/test/scala/firrtlTests/WidthSpec.scala | 20 ++++++++++++++++++++
 1 file changed, 20 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 4c9ad687..d1b16bb9 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -84,4 +84,24 @@ class WidthSpec extends FirrtlFlatSpec {
     val check = Seq( "output z : SInt<5>")
     executeTest(input, check, passes)
   }
+  "Dshl by 32 bits" should "result in an error" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm,
+      ResolveKinds,
+      InferTypes,
+      CheckTypes,
+      InferWidths,
+      CheckWidths)
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input x: UInt<3>
+        |    input y: UInt<32>
+        |    output z: UInt
+        |    z <= dshl(x, y)""".stripMargin
+    intercept[CheckWidths.WidthTooBig] {
+      executeTest(input, Nil, passes)
+    }
+  }
 }
-- 
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