From a029b9bbb339b9b9fb90959a0b0fbe1467fe4b18 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Mon, 14 Nov 2016 15:00:38 -0800
Subject: Fix wrong omitting same clocked nondirect children (#374)

* Fix wrong omitting same clocked nondirect children

* Minor style fixes
---
 src/test/scala/firrtlTests/ClockListTests.scala | 33 ++++++++++++++++++++++++-
 1 file changed, 32 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ClockListTests.scala b/src/test/scala/firrtlTests/ClockListTests.scala
index 534aab89..ddad7235 100644
--- a/src/test/scala/firrtlTests/ClockListTests.scala
+++ b/src/test/scala/firrtlTests/ClockListTests.scala
@@ -82,6 +82,37 @@ class ClockListTests extends FirrtlFlatSpec {
     }
     val writer = new StringWriter()
     val retC = new ClockList("HTop", writer).run(c)
-    (writer.toString()) should be (check)
+    (writer.toString) should be (check)
+  }
+  "A->B->C, and A.clock == C.clock" should "still emit C.clock origin" in {
+    val input =
+      """circuit A :
+        |  module A :
+        |    input clock: Clock
+        |    input clkB: Clock
+        |    inst b of B
+        |    b.clock <= clkB
+        |    b.clkC <= clock
+        |  module B :
+        |    input clock: Clock
+        |    input clkC: Clock
+        |    inst c of C
+        |    c.clock <= clkC
+        |  module C :
+        |    input clock: Clock
+        |    reg r: UInt<5>, clock
+        |""".stripMargin
+    val check = 
+  """Sourcelist: List(clock, clkB) 
+    |Good Origin of clock is clock
+    |Good Origin of b.clock is clkB
+    |Good Origin of b$c.clock is clock
+    |""".stripMargin
+    val c = passes.foldLeft(parse(input)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+    val writer = new StringWriter()
+    val retC = new ClockList("A", writer).run(c)
+    (writer.toString) should be (check)
   }
 }
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