From 9ff347c48eef530be9cbf1f8e5bbfb9ed053d182 Mon Sep 17 00:00:00 2001 From: Albert Chen Date: Fri, 19 Jun 2020 17:03:37 -0700 Subject: RemoveIntervals: invalidate InferTypes and ResolveKinds (#1689) --- src/test/scala/firrtlTests/LoweringCompilersSpec.scala | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala index b9143b26..cc4914f2 100644 --- a/src/test/scala/firrtlTests/LoweringCompilersSpec.scala +++ b/src/test/scala/firrtlTests/LoweringCompilersSpec.scala @@ -171,7 +171,9 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { Del(13), Add(12, Seq(Dependency(firrtl.passes.ResolveFlows), Dependency[firrtl.passes.InferWidths])), - Del(14) + Del(14), + Add(15, Seq(Dependency(firrtl.passes.ResolveKinds), + Dependency(firrtl.passes.InferTypes))) ) compare(legacyTransforms(new HighFirrtlToMiddleFirrtl), tm, patches) } @@ -349,7 +351,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { Seq(new Transforms.LowToLow, new firrtl.MinimumVerilogEmitter) val tm = (new TransformManager(Seq(Dependency[firrtl.MinimumVerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( - Add(60, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) + Add(62, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) compare(expected, tm, patches) } @@ -360,7 +362,7 @@ class LoweringCompilersSpec extends FlatSpec with Matchers { Seq(new Transforms.LowToLow, new firrtl.VerilogEmitter) val tm = (new TransformManager(Seq(Dependency[firrtl.VerilogEmitter], Dependency[Transforms.LowToLow]))) val patches = Seq( - Add(67, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) + Add(69, Seq(Dependency[firrtl.transforms.LegalizeAndReductionsTransform])) ) compare(expected, tm, patches) } -- cgit v1.2.3