From 98a23c0c1fe018c0899d26da5bfd18fb1e0bcab5 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Thu, 6 Feb 2020 16:29:58 -0800
Subject: Better register const prop through speculative de-optimization

* Fixes #1240
* Add failing reg const prop test case from #1240
---
 .../firrtlTests/ConstantPropagationTests.scala     | 23 ++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
index af186cda..99b8c2f0 100644
--- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala
+++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala
@@ -1148,6 +1148,29 @@ class ConstantPropagationIntegrationSpec extends LowTransformSpec {
     execute(input, check, Seq.empty)
   }
 
+  "Const prop of registers" should "do limited speculative expansion of optimized muxes to absorb bigger cones" in {
+      val input =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    input reset : UInt<1>
+          |    input en : UInt<1>
+          |    output out : UInt<1>
+          |    reg r : UInt<1>, clock
+          |    when en :
+          |      r <= UInt<1>(1)
+          |    out <= r""".stripMargin
+      val check =
+        """circuit Top :
+          |  module Top :
+          |    input clock : Clock
+          |    input reset : UInt<1>
+          |    input en : UInt<1>
+          |    output out : UInt<1>
+          |    out <= UInt<1>("h1")""".stripMargin
+    execute(input, check, Seq.empty)
+  }
+
   "A register with constant reset and all connection to either itself or the same constant" should "be replaced with that constant" in {
       val input =
         """circuit Top :
-- 
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