From 8653fd628f83c1bcb329dd37844ddfdb8f4cf206 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Wed, 15 Apr 2020 16:41:52 -0700
Subject: Add test cases for illegal casts to AsyncReset / Clock

---
 src/test/scala/firrtlTests/WidthSpec.scala | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/WidthSpec.scala b/src/test/scala/firrtlTests/WidthSpec.scala
index 4d04ed66..4b0bc5e5 100644
--- a/src/test/scala/firrtlTests/WidthSpec.scala
+++ b/src/test/scala/firrtlTests/WidthSpec.scala
@@ -68,6 +68,28 @@ class WidthSpec extends FirrtlFlatSpec {
     }
   }
 
+  "Casting a multi-bit signal to Clock" should "result in error" in {
+    val input =
+      s"""circuit Unit :
+         |  module Unit :
+         |    input i: UInt<2>
+         |    node x = asClock(i)""".stripMargin
+    intercept[CheckWidths.MultiBitAsClock] {
+        executeTest(input, Nil, inferAndCheckPasses)
+    }
+  }
+
+  "Casting a multi-bit signal to AsyncReset" should "result in error" in {
+    val input =
+      s"""circuit Unit :
+         |  module Unit :
+         |    input i: UInt<2>
+         |    node x = asAsyncReset(i)""".stripMargin
+    intercept[CheckWidths.MultiBitAsAsyncReset] {
+        executeTest(input, Nil, inferAndCheckPasses)
+    }
+  }
+
   "Width >= MaxWidth" should "result in an error" in {
     val input =
      s"""circuit Unit :
-- 
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