From 7c49fa1726ab1860fbb3616156467807de2d7e3c Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Wed, 6 Jun 2018 21:13:24 -0700
Subject: ConstProp attached wires if there is also a port (#818)

This enables the pattern of attaching "through" a wire to give better
Verilog that also works in Verilator

Use WrappedExpression when combining attaches in ExpandWhens
to ensure no duplication of references in resulting, combined attaches
---
 src/test/scala/firrtlTests/AttachSpec.scala | 32 +++++++++++++++++++++++------
 1 file changed, 26 insertions(+), 6 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/AttachSpec.scala b/src/test/scala/firrtlTests/AttachSpec.scala
index c9c609df..9bf5fefd 100644
--- a/src/test/scala/firrtlTests/AttachSpec.scala
+++ b/src/test/scala/firrtlTests/AttachSpec.scala
@@ -107,6 +107,31 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
     executeTest(input, check, compiler, Seq(dontTouch("Attaching.x")))
   }
 
+  it should "attach port to submodule port through a wire" in {
+    val compiler = new VerilogCompiler
+    val input =
+      """circuit Attaching :
+         |  module Attaching :
+         |    input an: Analog<3>
+         |    wire x: Analog
+         |    inst a of A
+         |    attach (x, a.an)
+         |    attach (x, an)
+         |  module A:
+         |    input an: Analog<3> """.stripMargin
+    val check =
+      """module Attaching(
+        |  inout [2:0] an
+        |);
+        |  A a (
+        |    .an(an)
+        |  );
+        |endmodule
+        |""".stripMargin.split("\n") map normalized
+    executeTest(input, check, compiler, Seq(dontTouch("Attaching.x")))
+  }
+
+
   it should "attach multiple sources" in {
     val compiler = new VerilogCompiler
     val input =
@@ -121,18 +146,13 @@ class InoutVerilogSpec extends FirrtlFlatSpec {
         |  inout  [2:0] a1,
         |  inout  [2:0] a2
         |);
-        |  wire [2:0] x;
         |  `ifdef SYNTHESIS
-        |    assign x = a1;
-        |    assign a1 = x;
-        |    assign x = a2;
-        |    assign a2 = x;
         |    assign a1 = a2;
         |    assign a2 = a1;
         |  `elsif verilator
         |    `error "Verilator does not support alias and thus cannot arbirarily connect bidirectional wires and ports"
         |  `else
-        |    alias x = a1 = a2;
+        |    alias a1 = a2;
         |  `endif
         |endmodule
         |""".stripMargin.split("\n") map normalized
-- 
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