From 89cbd83265c5bfb3968865ebaddf79efb4f47050 Mon Sep 17 00:00:00 2001
From: jackkoenig
Date: Wed, 27 Apr 2016 00:32:38 -0700
Subject: Add integration test for single-ported memory

---
 src/test/scala/firrtlTests/IntegrationSpec.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/IntegrationSpec.scala b/src/test/scala/firrtlTests/IntegrationSpec.scala
index 13e289d5..df4104a8 100644
--- a/src/test/scala/firrtlTests/IntegrationSpec.scala
+++ b/src/test/scala/firrtlTests/IntegrationSpec.scala
@@ -35,7 +35,8 @@ class IntegrationSpec extends FirrtlPropSpec {
   case class Test(name: String, dir: String)
 
   val runTests = Seq(Test("GCDTester", "/integration"),
-                     Test("RightShiftTester", "/integration"))
+                     Test("RightShiftTester", "/integration"),
+                     Test("MemTester", "/integration"))
       
 
   runTests foreach { test =>
-- 
cgit v1.2.3


From 243ff24f8eb9aae18bb0c7afe4f4c1e6cd66c084 Mon Sep 17 00:00:00 2001
From: Colin Schmidt
Date: Tue, 19 Apr 2016 09:51:24 -0700
Subject: add better type mismatch error message

also check for it int unittest
---
 src/test/scala/firrtlTests/UnitTests.scala | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index cee2c15d..dac8a40f 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -60,11 +60,12 @@ class UnitTests extends FirrtlFlatSpec {
         |    input y: {a : UInt<1>}
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
-    intercept[PassExceptions] {
+    val thrown = intercept[PassExceptions] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
+    assert(thrown.getMessage contains "Type mismatch. Cannot connect")
   }
 
   "Initializing a register with a different type" should "throw an exception" in {
-- 
cgit v1.2.3


From f9e8895b73aeec9bb71449f8e3d0e6f7e7a0a478 Mon Sep 17 00:00:00 2001
From: azidar
Date: Tue, 24 May 2016 10:17:51 -0700
Subject: Added Errors class and fixed tests.

Canonicalizes catching/throwing PassExceptions.
---
 src/test/scala/firrtlTests/CheckSpec.scala | 2 +-
 src/test/scala/firrtlTests/UnitTests.scala | 5 ++---
 2 files changed, 3 insertions(+), 4 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index ea0767bb..5c1b1a67 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -19,7 +19,7 @@ class CheckSpec extends FlatSpec with Matchers {
         |      depth => 32
         |      read-latency => 0
         |      write-latency => 1""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckHighForm.MemWithFlipException] {
       passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index dac8a40f..98693c61 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -60,12 +60,11 @@ class UnitTests extends FirrtlFlatSpec {
         |    input y: {a : UInt<1>}
         |    output x: {a : UInt<1>, b : UInt<1>}
         |    x <= y""".stripMargin
-    val thrown = intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidConnect] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
     }
-    assert(thrown.getMessage contains "Type mismatch. Cannot connect")
   }
 
   "Initializing a register with a different type" should "throw an exception" in {
@@ -83,7 +82,7 @@ class UnitTests extends FirrtlFlatSpec {
        |    wire x : { valid : UInt<1> }
        |    reg y : { valid : UInt<1>, bits : UInt<3> }, clk with :
        |      reset => (reset, x)""".stripMargin
-    intercept[PassExceptions] {
+    intercept[CheckTypes.InvalidRegInit] {
       passes.foldLeft(parse(input)) {
         (c: Circuit, p: Pass) => p.run(c)
       }
-- 
cgit v1.2.3