From 76862eb88adb8a056534fe937f2d7e9353feee94 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Wed, 27 Feb 2019 11:10:31 -0800
Subject: Add --nodedup option to facilitate FIRRTL to verilog regression
 testing. (#1035)

* Add --nodedup option to facilitate FIRRTL to verilog regression testing.

* Short-circuit the DedupModules transform if NoCircuitDedupAnnotation exists.
---
 .../scala/firrtlTests/transforms/DedupTests.scala  | 27 +++++++++++++++++++++-
 1 file changed, 26 insertions(+), 1 deletion(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/transforms/DedupTests.scala b/src/test/scala/firrtlTests/transforms/DedupTests.scala
index 9b949274..971e8a1d 100644
--- a/src/test/scala/firrtlTests/transforms/DedupTests.scala
+++ b/src/test/scala/firrtlTests/transforms/DedupTests.scala
@@ -5,7 +5,7 @@ package transforms
 
 import firrtl.RenameMap
 import firrtl.annotations._
-import firrtl.transforms.DedupModules
+import firrtl.transforms.{DedupModules, NoCircuitDedupAnnotation}
 
 
 /**
@@ -553,5 +553,30 @@ class DedupModuleTests extends HighTransformSpec {
       """.stripMargin
     execute(input, check, Seq.empty)
   }
+  "modules" should "not be deduped if the NoCircuitDedupAnnotation (or --no-dedup option) is supplied" in {
+    val input =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    val check =
+      """circuit main:
+        |  module dupe:
+        |    input in: UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+        |  module main:
+        |    input in:  UInt<8>
+        |    output out: UInt<8>
+        |    out <= in
+      """.stripMargin
+    execute(input, check, Seq(NoCircuitDedupAnnotation))
+  }
 }
 
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