From 6ef7ad148ff491c06d417d417e2134da7ff49ef7 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Fri, 25 Jan 2019 14:53:13 -0500 Subject: Add "mverilog" and "sverilog" DriverSpec tests This adds runs of the minimum Verilog compiler and SystemVerilog compiler in DriverSpec. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/DriverSpec.scala | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/DriverSpec.scala b/src/test/scala/firrtlTests/DriverSpec.scala index 545bf09a..ae1e08e7 100644 --- a/src/test/scala/firrtlTests/DriverSpec.scala +++ b/src/test/scala/firrtlTests/DriverSpec.scala @@ -371,7 +371,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> "./Top.lo.fir", "high" -> "./Top.hi.fir", "middle" -> "./Top.mid.fir", - "verilog" -> "./Top.v" + "verilog" -> "./Top.v", + "mverilog" -> "./Top.v", + "sverilog" -> "./Top.sv" ).foreach { case (compilerName, expectedOutputFileName) => val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { commonOptions = CommonOptions(topName = "Top") @@ -391,7 +393,9 @@ class DriverSpec extends FreeSpec with Matchers with BackendCompilationUtilities "low" -> Seq("./Top.lo.fir", "./Child.lo.fir"), "high" -> Seq("./Top.hi.fir", "./Child.hi.fir"), "middle" -> Seq("./Top.mid.fir", "./Child.mid.fir"), - "verilog" -> Seq("./Top.v", "./Child.v") + "verilog" -> Seq("./Top.v", "./Child.v"), + "mverilog" -> Seq("./Top.v", "./Child.v"), + "sverilog" -> Seq("./Top.sv", "./Child.sv") ).foreach { case (compilerName, expectedOutputFileNames) => println(s"$compilerName -> $expectedOutputFileNames") val manager = new ExecutionOptionsManager("test") with HasFirrtlOptions { -- cgit v1.2.3