From 6db311b39b2330637e5bf47f308e68292eca1381 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Tue, 4 May 2021 13:18:51 -0700 Subject: Make MustDeduplicateAnnotation deletable (#2215) --- .../firrtlTests/transforms/MustDedupSpec.scala | 34 ++++++++++++++++++++++ 1 file changed, 34 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/transforms/MustDedupSpec.scala b/src/test/scala/firrtlTests/transforms/MustDedupSpec.scala index 2f633e0e..5d25321e 100644 --- a/src/test/scala/firrtlTests/transforms/MustDedupSpec.scala +++ b/src/test/scala/firrtlTests/transforms/MustDedupSpec.scala @@ -264,4 +264,38 @@ class MustDedupSpec extends AnyFeatureSpec with FirrtlMatchers with GivenWhenThe (new firrtl.stage.FirrtlPhase).transform(annos) } } + + Feature("When you have unused modules that should dedup, and they do") { + val text = """ + |circuit A : + | module B : + | output io : { flip in : UInt<8>, out : UInt<8> } + | io.out <= io.in + | module B_1 : + | output io : { flip in : UInt<8>, out : UInt<8> } + | io.out <= io.in + | module A : + | output io : { flip in : UInt<8>, out : UInt<8> } + | inst b of B + | inst b_1 of B_1 + | b.io.in <= io.in + | b_1.io.in <= io.in + | io.out <= and(io.in, UInt(123)) + """.stripMargin + val top = CircuitTarget("A") + val bdedup = MustDeduplicateAnnotation(Seq(top.module("B"), top.module("B_1"))) + + Scenario("MustDeduplicateAnnotation should be deleted gracefully") { + val testDir = createTestDirectory("must_dedup") + val annos = Seq( + TargetDirAnnotation(testDir.toString), + FirrtlSourceAnnotation(text), + RunFirrtlTransformAnnotation(new MustDeduplicateTransform), + bdedup + ) + + val resAnnos = (new firrtl.stage.FirrtlPhase).transform(annos) + resAnnos.collectFirst { case a: MustDeduplicateTransform => a } should be(None) + } + } } -- cgit v1.2.3