From 6c8f327e681dee0b3e72399eb0a2dfceed3d0ad7 Mon Sep 17 00:00:00 2001 From: Donggyu Date: Wed, 3 Aug 2016 09:00:10 -0700 Subject: fixes small mistakes in serialize (#216) --- .../scala/firrtlTests/InferReadWriteSpec.scala | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/InferReadWriteSpec.scala b/src/test/scala/firrtlTests/InferReadWriteSpec.scala index 93f73741..7e3383b2 100644 --- a/src/test/scala/firrtlTests/InferReadWriteSpec.scala +++ b/src/test/scala/firrtlTests/InferReadWriteSpec.scala @@ -36,25 +36,24 @@ import Annotations._ class InferReadWriteSpec extends SimpleTransformSpec { object InferReadWriteCheckPass extends Pass { val name = "Check Infer ReadWrite Ports" - var foundReadWrite = false - def findReadWrite(s: Statement): Unit = s match { - case s: DefMemory if s.readLatency > 0 => - foundReadWrite = s.name == "mem" && s.readwriters.size == 1 + def findReadWrite(s: Statement): Boolean = s match { + case s: DefMemory if s.readLatency > 0 && s.readwriters.size == 1 => + s.name == "mem" && s.readwriters.head == "rw_0" case s: Block => - s.stmts foreach findReadWrite - case _ => + s.stmts exists findReadWrite + case _ => false } def run (c: Circuit) = { val errors = new Errors - c.modules foreach { + val foundReadWrite = c.modules exists { case m: Module => findReadWrite(m.body) - case m: ExtModule => m + case m: ExtModule => false } if (!foundReadWrite) { errors append new PassException("Readwrite ports are not found!") + errors.trigger } - errors.trigger c } } @@ -99,6 +98,9 @@ circuit sram6t : """.stripMargin val annotaitonMap = AnnotationMap(Seq(InferReadWriteAnnotation("sram6t", TransID(-1)))) - compile(parse(input), annotaitonMap, new java.io.StringWriter) + val writer = new java.io.StringWriter + compile(parse(input), annotaitonMap, writer) + // Check correctness of firrtl + parse(writer.toString) } } -- cgit v1.2.3