From 6b030c982c11a330c81daeee7b798f6c147b9a05 Mon Sep 17 00:00:00 2001 From: Jack Koenig Date: Sun, 26 Feb 2017 18:34:30 -0800 Subject: Align types and names of ports in emitted Verilog (#463) --- .../scala/firrtlTests/VerilogEmitterTests.scala | 43 ++++++++++++++++++++++ 1 file changed, 43 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/VerilogEmitterTests.scala b/src/test/scala/firrtlTests/VerilogEmitterTests.scala index 41fd6e41..862a9605 100644 --- a/src/test/scala/firrtlTests/VerilogEmitterTests.scala +++ b/src/test/scala/firrtlTests/VerilogEmitterTests.scala @@ -96,3 +96,46 @@ class DoPrimVerilog extends FirrtlFlatSpec { executeTest(input, check, compiler) } } + +class VerilogEmitterSpec extends FirrtlFlatSpec { + "Ports" should "emit with widths aligned and names aligned" in { + val compiler = new VerilogCompiler + val input = + """circuit Test : + | module Test : + | input a : UInt<25000> + | output b : UInt + | input c : UInt<32> + | output d : UInt + | input e : UInt<1> + | input f : Analog<32> + | b <= a + | d <= add(c, e) + |""".stripMargin + val check = Seq( + " input [24999:0] a,", + " output [24999:0] b,", + " input [31:0] c,", + " output [32:0] d,", + " input e,", + " inout [31:0] f" + ) + // We don't use executeTest because we care about the spacing in the result + val writer = new java.io.StringWriter + compiler.compile(CircuitState(parse(input), ChirrtlForm), writer) + val lines = writer.toString.split("\n") + for (c <- check) { + lines should contain (c) + } + } + "The Verilog Emitter" should "support Modules with no ports" in { + val compiler = new VerilogCompiler + val input = + """circuit Test : + | module Test : + | wire x : UInt<32> + | x <= UInt(0) + """.stripMargin + compiler.compile(CircuitState(parse(input), ChirrtlForm), new java.io.StringWriter) + } +} -- cgit v1.2.3