From 6aea3924fb48cbb4c1be217630c60be39b243ff1 Mon Sep 17 00:00:00 2001 From: azidar Date: Thu, 4 Aug 2016 15:15:00 -0700 Subject: Addd check: bits, tail, head arg width --- src/test/scala/firrtlTests/UnitTests.scala | 57 ++++++++++++++++++++++++++++++ 1 file changed, 57 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala index bc8db897..2d1bbdc1 100644 --- a/src/test/scala/firrtlTests/UnitTests.scala +++ b/src/test/scala/firrtlTests/UnitTests.scala @@ -232,4 +232,61 @@ class UnitTests extends FirrtlFlatSpec { ) executeTest(input, check, passes) } + + "Oversized bit select" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + ResolveGenders, + InferWidths, + CheckWidths) + val input = + """circuit Unit : + | module Unit : + | node x = bits(UInt(1), 100, 0)""".stripMargin + intercept[CheckWidths.BitsWidthException] { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + } + + "Oversized head select" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + ResolveGenders, + InferWidths, + CheckWidths) + val input = + """circuit Unit : + | module Unit : + | node x = head(UInt(1), 100)""".stripMargin + intercept[CheckWidths.HeadWidthException] { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + } + + "Oversized tail select" should "throw an exception" in { + val passes = Seq( + ToWorkingIR, + ResolveKinds, + InferTypes, + ResolveGenders, + InferWidths, + CheckWidths) + val input = + """circuit Unit : + | module Unit : + | node x = tail(UInt(1), 100)""".stripMargin + intercept[CheckWidths.TailWidthException] { + passes.foldLeft(Parser.parse(input.split("\n").toIterator)) { + (c: Circuit, p: Pass) => p.run(c) + } + } + } } -- cgit v1.2.3