From 698a9dca52f819aca6309e3b03f2420a71bc89a6 Mon Sep 17 00:00:00 2001 From: Schuyler Eldridge Date: Tue, 19 Jan 2021 22:49:31 -0500 Subject: Add --dont-fold option to disable folding prim ops (#2040) This adds a --dont-fold options (backed by a DisableFold annotation) that lets a user specify primitive operations which should never be folded. This feature lets a user disable certain folds which may be allowable in FIRRTL (or by any sane synthesis tool), but due to inane Verilog language design causes formal equivalence tools to fail due to the fold. Add a test that a user can disable `a / a -> 1` with a DisableFold(PrimOps.Div) annotation. Signed-off-by: Schuyler Eldridge --- src/test/scala/firrtlTests/ConstantPropagationTests.scala | 12 ++++++++++++ 1 file changed, 12 insertions(+) (limited to 'src/test') diff --git a/src/test/scala/firrtlTests/ConstantPropagationTests.scala b/src/test/scala/firrtlTests/ConstantPropagationTests.scala index 94973042..28c1d823 100644 --- a/src/test/scala/firrtlTests/ConstantPropagationTests.scala +++ b/src/test/scala/firrtlTests/ConstantPropagationTests.scala @@ -7,6 +7,7 @@ import firrtl.passes._ import firrtl.transforms._ import firrtl.testutils._ import firrtl.annotations.Annotation +import firrtl.stage.DisableFold class ConstantPropagationSpec extends FirrtlFlatSpec { val transforms: Seq[Transform] = @@ -798,6 +799,17 @@ class ConstantPropagationSingleModule extends ConstantPropagationSpec { castCheck("Clock", "asClock") castCheck("AsyncReset", "asAsyncReset") } + + /* */ + "The rule a / a -> 1" should "be ignored if division folds are disabled" in { + val input = + """circuit foo: + | module foo: + | input a: UInt<8> + | output b: UInt<8> + | b <= div(a, a)""".stripMargin + (parse(exec(input, Seq(DisableFold(PrimOps.Div))))) should be(parse(input)) + } } // More sophisticated tests of the full compiler -- cgit v1.2.3