From 51fb6db4fc82aba80650f6e98267b34fcea14122 Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Tue, 13 Jun 2017 13:23:31 -0700
Subject: Make ExpandWhens delete 'is invalid' for attached Analog components

Also add tests for what should happen to 'is invalid' in ExpandWhens
Fixes #606
---
 src/test/scala/firrtlTests/ExpandWhensSpec.scala | 44 ++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ExpandWhensSpec.scala b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
index 4911f619..66f39a3d 100644
--- a/src/test/scala/firrtlTests/ExpandWhensSpec.scala
+++ b/src/test/scala/firrtlTests/ExpandWhensSpec.scala
@@ -78,6 +78,50 @@ class ExpandWhensSpec extends FirrtlFlatSpec {
     val check = "VOID"
     executeTest(input, check, true)
   }
+  it should "replace 'is invalid' with validif for wires that have a connection" in {
+    val input =
+      """|circuit Tester :
+         |  module Tester :
+         |    input p : UInt<1>
+         |    output out : UInt
+         |    wire w : UInt<32>
+         |    w is invalid
+         |    out <= w
+         |    when p :
+         |      w <= UInt(123)
+         """.stripMargin
+    val check = "validif(p"
+    executeTest(input, check, true)
+  }
+  it should "leave 'is invalid' for wires that don't have a connection" in {
+    val input =
+      """|circuit Tester :
+         |  module Tester :
+         |    input p : UInt<1>
+         |    output out : UInt
+         |    wire w : UInt<32>
+         |    w is invalid
+         |    out <= w
+         """.stripMargin
+    val check = "w is invalid"
+    executeTest(input, check, true)
+  }
+  it should "delete 'is invalid' for attached Analog wires" in {
+    val input =
+      """|circuit Tester :
+         |  extmodule Child :
+         |    input bus : Analog<32>
+         |  module Tester :
+         |    input bus : Analog<32>
+         |    inst c of Child
+         |    wire w : Analog<32>
+         |    attach (w, bus)
+         |    attach (w, c.bus)
+         |    w is invalid
+         """.stripMargin
+    val check = "w is invalid"
+    executeTest(input, check, false)
+  }
 }
 
 class ExpandWhensExecutionTest extends ExecutionTest("ExpandWhens", "/passes/ExpandWhens")
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