From 4e77c5e14a05cedda621a4acdbc435bed23a202d Mon Sep 17 00:00:00 2001
From: Jack Koenig
Date: Thu, 31 Jan 2019 17:10:50 -0800
Subject: Use apache commons for string escaping instead of reflection (#1008)

---
 src/test/scala/firrtlTests/StringSpec.scala | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/StringSpec.scala b/src/test/scala/firrtlTests/StringSpec.scala
index f1f0bbde..208d9e6c 100644
--- a/src/test/scala/firrtlTests/StringSpec.scala
+++ b/src/test/scala/firrtlTests/StringSpec.scala
@@ -59,16 +59,16 @@ class StringSpec extends FirrtlPropSpec {
 
   // Whitelist is [0x20 - 0x7e]
   val whitelist =
-    """ !\"#$%&\'()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ""" +
+    """ !\"#$%&\''()*+,-./0123456789:;<=>?@ABCDEFGHIJKLMNOPQRSTUVWXYZ""" +
     """[\\]^_`abcdefghijklmnopqrstuvwxyz{|}~"""
 
   property(s"Character whitelist should be supported: [$whitelist] ") {
     val lit = StringLit.unescape(whitelist)
+    // We accept \' but don't bother escaping it ourselves
+    val res = whitelist.replaceAll("""\\'""", "'")
     // Check result
-    assert(lit.serialize == whitelist)
-    // Scala likes to escape ' as \', Verilog doesn't
-    val verilogWhitelist = whitelist.replaceAll("""\\'""", "'")
-    assert(lit.verilogEscape.tail.init == verilogWhitelist)
+    assert(lit.serialize == res)
+    assert(lit.verilogEscape.tail.init == res)
   }
 
   // Valid escapes = \n, \t, \\, \", \'
-- 
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