From 488aec3a35b6fa99a8150702128c9c1e87246644 Mon Sep 17 00:00:00 2001
From: Donggyu Kim
Date: Thu, 25 Aug 2016 18:17:11 -0700
Subject: remove Utils.{AND, OR, NOT, EQV}

hidden const props not desirable
---
 src/test/scala/firrtlTests/UnitTests.scala | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 2d1bbdc1..7feb4a00 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -203,7 +203,8 @@ class UnitTests extends FirrtlFlatSpec {
       InferWidths,
       PullMuxes,
       ExpandConnects,
-      RemoveAccesses
+      RemoveAccesses,
+      ConstProp
     )
     val input =
       """circuit AssignViaDeref : 
@@ -221,7 +222,7 @@ class UnitTests extends FirrtlFlatSpec {
      val check = Seq(
        """wire GEN_0 : { a : UInt<8>}""",
        """GEN_0.a <= table[0].a""",
-       """when eq(UInt<1>("h1"), UInt<1>("h1")) :""",
+       """when UInt<1>("h1") :""",
        """GEN_0.a <= table[1].a""",
        """wire GEN_1 : UInt<8>""",
        """when eq(UInt<1>("h0"), GEN_0.a) :""",
-- 
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