From 0441a6df1eafd5db99c5cbcc0a07c5a6cb37f975 Mon Sep 17 00:00:00 2001
From: azidar
Date: Thu, 21 Jul 2016 13:57:13 -0700
Subject: Added a Chirrtl check for undeclared wires, etc.

---
 src/test/scala/firrtlTests/ChirrtlSpec.scala | 59 +++++++++++++++++++---------
 1 file changed, 40 insertions(+), 19 deletions(-)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ChirrtlSpec.scala b/src/test/scala/firrtlTests/ChirrtlSpec.scala
index d3e02ff1..a24cd9fa 100644
--- a/src/test/scala/firrtlTests/ChirrtlSpec.scala
+++ b/src/test/scala/firrtlTests/ChirrtlSpec.scala
@@ -35,27 +35,28 @@ import firrtl.ir.Circuit
 import firrtl.passes._
 
 class ChirrtlSpec extends FirrtlFlatSpec {
+  def passes = Seq(
+    CheckChirrtl,
+    CInferTypes,
+    CInferMDir,
+    RemoveCHIRRTL,
+    ToWorkingIR,            
+    CheckHighForm,
+    ResolveKinds,
+    InferTypes,
+    CheckTypes,
+    ResolveGenders,
+    CheckGenders,
+    InferWidths,
+    CheckWidths,
+    PullMuxes,
+    ExpandConnects,
+    RemoveAccesses,
+    ExpandWhens,
+    CheckInitialization
+  )
 
   "Chirrtl memories" should "allow ports with clocks defined after the memory" in {
-    val passes = Seq(
-      CInferTypes,
-      CInferMDir,
-      RemoveCHIRRTL,
-      ToWorkingIR,            
-      CheckHighForm,
-      ResolveKinds,
-      InferTypes,
-      CheckTypes,
-      ResolveGenders,
-      CheckGenders,
-      InferWidths,
-      CheckWidths,
-      PullMuxes,
-      ExpandConnects,
-      RemoveAccesses,
-      ExpandWhens,
-      CheckInitialization
-    )
     val input =
      """circuit Unit :
        |  module Unit :
@@ -73,6 +74,26 @@ class ChirrtlSpec extends FirrtlFlatSpec {
     }
   }
 
+  "Chirrtl" should "catch undeclared wires" in {
+    val input =
+     """circuit Unit :
+       |  module Unit :
+       |    input clk : Clock
+       |    smem ram : UInt<32>[128]
+       |    node newClock = clk
+       |    infer mport x = ram[UInt(2)], newClock
+       |    x <= UInt(3)
+       |    when UInt(1) :
+       |      infer mport y = ram[UInt(4)], newClock
+       |      y <= z
+       """.stripMargin
+    intercept[PassException] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
   it should "compile and run" in {
     runFirrtlTest("ChirrtlMems", "/features")
   }
-- 
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