From 430a8afb2cf42e9eef438c7ea38934113de0bbcf Mon Sep 17 00:00:00 2001
From: chick
Date: Thu, 24 May 2018 13:34:25 -0700
Subject: Makes ExpandWhens preserve connect Infos

* Collects Infos found for symbols
* Merges multiple sources for symbol into MultiInfo
* Restores these Infos on connect statements.
* Add test showing preserved Infos
* Changed ++ methods on the Info sub-classes
  * Ignore NoInfo being added
  * Fixed way adding was implemented in MultiInfo
* Made InfoMap a class which defines the default value function
---
 src/test/scala/firrtlTests/InfoSpec.scala | 40 +++++++++++++++++++++++++++++++
 1 file changed, 40 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/InfoSpec.scala b/src/test/scala/firrtlTests/InfoSpec.scala
index 8d49d753..dbc997cd 100644
--- a/src/test/scala/firrtlTests/InfoSpec.scala
+++ b/src/test/scala/firrtlTests/InfoSpec.scala
@@ -117,4 +117,44 @@ class InfoSpec extends FirrtlFlatSpec {
     result should containTree { case WDefInstance(Info1, "c", "Child", _) => true }
     result should containLine (s"Child c ( //$Info1")
   }
+
+  "source locators" should "be propagated through ExpandWhens" in {
+    val input = """
+     |;buildInfoPackage: chisel3, version: 3.1-SNAPSHOT, scalaVersion: 2.11.7, sbtVersion: 0.13.11, builtAtString: 2016-11-26 18:48:38.030, builtAtMillis: 1480186118030
+     |circuit GCD :
+     |  module GCD :
+     |    input clock : Clock
+     |    input reset : UInt<1>
+     |    output io : {flip a : UInt<32>, flip b : UInt<32>, flip e : UInt<1>, z : UInt<32>, v : UInt<1>}
+     |
+     |    io is invalid
+     |    io is invalid
+     |    reg x : UInt<32>, clock @[GCD.scala 15:14]
+     |    reg y : UInt<32>, clock @[GCD.scala 16:14]
+     |    node _T_14 = gt(x, y) @[GCD.scala 17:11]
+     |    when _T_14 : @[GCD.scala 17:18]
+     |      node _T_15 = sub(x, y) @[GCD.scala 17:27]
+     |      node _T_16 = tail(_T_15, 1) @[GCD.scala 17:27]
+     |      x <= _T_16 @[GCD.scala 17:22]
+     |      skip @[GCD.scala 17:18]
+     |    node _T_18 = eq(_T_14, UInt<1>("h00")) @[GCD.scala 17:18]
+     |    when _T_18 : @[GCD.scala 18:18]
+     |      node _T_19 = sub(y, x) @[GCD.scala 18:27]
+     |      node _T_20 = tail(_T_19, 1) @[GCD.scala 18:27]
+     |      y <= _T_20 @[GCD.scala 18:22]
+     |      skip @[GCD.scala 18:18]
+     |    when io.e : @[GCD.scala 19:15]
+     |      x <= io.a @[GCD.scala 19:19]
+     |      y <= io.b @[GCD.scala 19:30]
+     |      skip @[GCD.scala 19:15]
+     |    io.z <= x @[GCD.scala 20:8]
+     |    node _T_22 = eq(y, UInt<1>("h00")) @[GCD.scala 21:13]
+     |    io.v <= _T_22 @[GCD.scala 21:8]
+     |
+      """.stripMargin
+
+    val result = (new LowFirrtlCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm), List.empty)
+    result should containLine ("x <= _GEN_2 @[GCD.scala 17:22 GCD.scala 19:19]")
+    result should containLine ("y <= _GEN_3 @[GCD.scala 18:22 GCD.scala 19:30]")
+  }
 }
-- 
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