From 94b28438d1658d0835122b8c27bbbf3753892475 Mon Sep 17 00:00:00 2001
From: chick
Date: Mon, 25 Jul 2016 11:39:54 -0700
Subject: Detects and flags cyclic module loops

---
 src/test/scala/firrtlTests/CheckSpec.scala | 116 +++++++++++++++++++++++++++++
 1 file changed, 116 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index 69645ddc..65873540 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -26,4 +26,120 @@ class CheckSpec extends FlatSpec with Matchers {
       }
     }
   }
+  "Instance loops a -> b -> a" should "be detected" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """
+        |circuit Foo :
+        |  module Foo :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst bar of Bar
+        |    bar.a <= a
+        |    b <= bar.b
+        |
+        |  module Bar :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst foo of Foo
+        |    foo.a <= a
+        |    b <= foo.b
+      """.stripMargin
+    intercept[CheckHighForm.InstanceLoop] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
+  "Instance loops a -> b -> c -> a" should "be detected" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """
+        |circuit Dog :
+        |  module Dog :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst bar of Cat
+        |    bar.a <= a
+        |    b <= bar.b
+        |
+        |  module Cat :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst ik of Ik
+        |    ik.a <= a
+        |    b <= ik.b
+        |
+        |  module Ik :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst foo of Dog
+        |    foo.a <= a
+        |    b <= foo.b
+        |      """.stripMargin
+    intercept[CheckHighForm.InstanceLoop] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
+  "Instance loops a -> a" should "be detected" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """
+        |circuit Apple :
+        |  module Apple :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst recurse_foo of Apple
+        |    recurse_foo.a <= a
+        |    b <= recurse_foo.b
+        |      """.stripMargin
+    intercept[CheckHighForm.InstanceLoop] {
+      passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+        (c: Circuit, p: Pass) => p.run(c)
+      }
+    }
+  }
+
+  "Instance loops should not have false positives" should "be detected" in {
+    val passes = Seq(
+      ToWorkingIR,
+      CheckHighForm)
+    val input =
+      """
+        |circuit Hammer :
+        |  module Hammer :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst bar of Chisel
+        |    bar.a <= a
+        |    b <= bar.b
+        |
+        |  module Chisel :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    inst ik of Saw
+        |    ik.a <= a
+        |    b <= ik.b
+        |
+        |  module Saw :
+        |    input a : UInt<32>
+        |    output b : UInt<32>
+        |    b <= a
+        |      """.stripMargin
+    passes.foldLeft(Parser.parse(input.split("\n").toIterator)) {
+      (c: Circuit, p: Pass) => p.run(c)
+    }
+
+  }
+
 }
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