From 384ad661dde15d1fc9c58da7a9fc2970b25528e9 Mon Sep 17 00:00:00 2001
From: Adam Izraelevitz
Date: Sat, 30 Sep 2017 09:21:13 -0700
Subject: Fixed zero width cat but (#651)

---
 src/test/scala/firrtlTests/ZeroWidthTests.scala | 44 +++++++++++++++++++++++++
 1 file changed, 44 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/ZeroWidthTests.scala b/src/test/scala/firrtlTests/ZeroWidthTests.scala
index 8c39dc1e..50385a80 100644
--- a/src/test/scala/firrtlTests/ZeroWidthTests.scala
+++ b/src/test/scala/firrtlTests/ZeroWidthTests.scala
@@ -132,6 +132,50 @@ class ZeroWidthTests extends FirrtlFlatSpec {
         |    node z = add(x, UInt<1>(0))""".stripMargin
       (parse(exec(input)).serialize) should be (parse(check).serialize)
   }
+  "Expression in cat with type <0>" should "be removed" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    node z = cat(x, y)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input x: UInt<1>
+        |    node z = x""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  "Nested cats with type <0>" should "be removed" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x: UInt<0>
+        |    input y: UInt<0>
+        |    input z: UInt<0>
+        |    node a = cat(cat(x, y), z)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    skip""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
+  "Nested cats where one has type <0>" should "be unaffected" in {
+    val input =
+      """circuit Top :
+        |  module Top :
+        |    input x: UInt<1>
+        |    input y: UInt<0>
+        |    input z: UInt<1>
+        |    node a = cat(cat(x, y), z)""".stripMargin
+    val check =
+      """circuit Top :
+        |  module Top :
+        |    input x: UInt<1>
+        |    input z: UInt<1>
+        |    node a = cat(x, z)""".stripMargin
+      (parse(exec(input)).serialize) should be (parse(check).serialize)
+  }
 }
 
 class ZeroWidthVerilog extends FirrtlFlatSpec {
-- 
cgit v1.2.3