From 3c1a8e88844f2df41a60f5a8902b61ccf67b1382 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Tue, 14 Apr 2020 14:06:53 -0700
Subject: Add Conditionally scoping tests to CheckSpec

* Add specific test for shadowing
---
 src/test/scala/firrtlTests/CheckSpec.scala | 47 ++++++++++++++++++++++++++++++
 1 file changed, 47 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/CheckSpec.scala b/src/test/scala/firrtlTests/CheckSpec.scala
index c622bde5..b49054ad 100644
--- a/src/test/scala/firrtlTests/CheckSpec.scala
+++ b/src/test/scala/firrtlTests/CheckSpec.scala
@@ -352,6 +352,53 @@ class CheckSpec extends AnyFlatSpec with Matchers {
     }
   }
 
+  "Conditionally statements" should "create a new scope" in {
+    val input =
+      s"""|circuit scopes:
+          |  module scopes:
+          |    input i: UInt<1>
+          |    output o: UInt<1>
+          |    when i:
+          |      node x = not(i)
+          |    o <= and(x, i)
+          |""".stripMargin
+    assertThrows[CheckHighForm.UndeclaredReferenceException] {
+      checkHighInput(input)
+    }
+  }
+
+  "Attempting to shadow a component name" should "throw an error" in {
+    val input =
+      s"""|circuit scopes:
+          |  module scopes:
+          |    input i: UInt<1>
+          |    output o: UInt<1>
+          |    wire x: UInt<1>
+          |    when i:
+          |      node x = not(i)
+          |    o <= and(x, i)
+          |""".stripMargin
+    assertThrows[CheckHighForm.NotUniqueException] {
+      checkHighInput(input)
+    }
+  }
+
+  "Conditionally statements" should "create separate consequent and alternate scopes" in {
+    val input =
+      s"""|circuit scopes:
+          |  module scopes:
+          |    input i: UInt<1>
+          |    output o: UInt<1>
+          |    o <= i
+          |    when i:
+          |      node x = not(i)
+          |    else:
+          |      o <= and(x, i)
+          |""".stripMargin
+    assertThrows[CheckHighForm.UndeclaredReferenceException] {
+      checkHighInput(input)
+    }
+  }
 }
 
 object CheckSpec {
-- 
cgit v1.2.3


From 1220a23ac9dfc26dbf5475ef064b644cdd1d7983 Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Tue, 14 Apr 2020 15:29:43 -0700
Subject: Fix out-of-scope reference in handwritten CHIRRTL mem test

---
 src/test/resources/features/ChirrtlMems.fir | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/test')

diff --git a/src/test/resources/features/ChirrtlMems.fir b/src/test/resources/features/ChirrtlMems.fir
index c51e3b78..de5b3cf3 100644
--- a/src/test/resources/features/ChirrtlMems.fir
+++ b/src/test/resources/features/ChirrtlMems.fir
@@ -14,13 +14,13 @@ circuit ChirrtlMems :
     raddr <= add(raddr, UInt(1))
     infer mport r = ram[raddr], newClock
 
+    reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
+    waddr <= add(waddr, UInt(1))
+
     when wen :
       node newerClock = clock
-      reg waddr : UInt<4>, clock with : (reset => (reset, UInt(0)))
-      waddr <= add(waddr, UInt(1))
       infer mport w = ram[waddr], newerClock
       w <= waddr
-
       when eq(waddr, UInt(0)) :
         raddr <= UInt(0)
 
-- 
cgit v1.2.3