From 24f81e828b70e2745c2fbd06a4694a9f054851e8 Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Tue, 26 Mar 2019 12:00:03 -0700
Subject: Add test for DCE of printf and stop

---
 src/test/scala/firrtlTests/DCETests.scala | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/DCETests.scala b/src/test/scala/firrtlTests/DCETests.scala
index a6def402..620cc5f3 100644
--- a/src/test/scala/firrtlTests/DCETests.scala
+++ b/src/test/scala/firrtlTests/DCETests.scala
@@ -449,6 +449,23 @@ class DCETests extends FirrtlFlatSpec {
     // Check for register update
     verilog should include regex ("""(?m)if \(a\) begin\n\s*r <= x;\s*end""")
   }
+
+  "Emitted Verilog" should "not contain dead print or stop statements" in {
+    val input = parse(
+      """circuit test :
+        |  module test :
+        |    input clock : Clock
+        |    when UInt<1>(0) :
+        |      printf(clock, UInt<1>(1), "o hai")
+        |      stop(clock, UInt<1>(1), 1)""".stripMargin
+    )
+
+    val state = CircuitState(input, ChirrtlForm)
+    val result = (new VerilogCompiler).compileAndEmit(state, List.empty)
+    val verilog = result.getEmittedCircuit.value
+    verilog shouldNot include regex ("""fwrite""")
+    verilog shouldNot include regex ("""fatal""")
+  }
 }
 
 class DCECommandLineSpec extends FirrtlFlatSpec {
-- 
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