From 1738c1ef0ac95fae25d52586b3b0348de80de2ff Mon Sep 17 00:00:00 2001
From: Andrew Waterman
Date: Wed, 23 Jan 2019 13:27:19 -0800
Subject: Improve Shl codegen; eliminate Shlw WIR node (#994)

* Improve Shl codegen; eliminate Shlw WIR node

If we emit shl(x, k) as {x, k'h0} instead of (x << k), then there's
no need for Verilog-specific padding in the PadWidths pass.  Avoiding
the redundant padding improves compiler/simulator performance and
renders Shlw unnecessary.

* [skip formal checks] Add test
---
 src/test/scala/firrtlTests/UnitTests.scala | 12 ++++++++++++
 1 file changed, 12 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/UnitTests.scala b/src/test/scala/firrtlTests/UnitTests.scala
index 2cf9c001..b3af920c 100644
--- a/src/test/scala/firrtlTests/UnitTests.scala
+++ b/src/test/scala/firrtlTests/UnitTests.scala
@@ -437,4 +437,16 @@ class UnitTests extends FirrtlFlatSpec {
 
     result should containTree { case Connect(_, `out`, mgen) => true }
   }
+
+  "Shl" should "be emitted in Verilog as concat" in {
+    val input =
+      """circuit Unit :
+        |  module Unit :
+        |    input in : UInt<4>
+        |    output out : UInt<8>
+        |    out <= shl(in, 4)
+        |""".stripMargin
+    val res = (new VerilogCompiler).compileAndEmit(CircuitState(parse(input), ChirrtlForm))
+    res should containLine ("assign out = {in, 4'h0};")
+  }
 }
-- 
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