From 14b9ead2ee028ba977e9c61eff962380d4e87d30 Mon Sep 17 00:00:00 2001
From: Schuyler Eldridge
Date: Fri, 3 May 2019 21:00:52 -0400
Subject: Add register init to RemoveWires dependencies (#1078)

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>---
 src/test/scala/firrtlTests/RemoveWiresSpec.scala | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/RemoveWiresSpec.scala b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
index e40a770b..06e5dccd 100644
--- a/src/test/scala/firrtlTests/RemoveWiresSpec.scala
+++ b/src/test/scala/firrtlTests/RemoveWiresSpec.scala
@@ -182,4 +182,20 @@ class RemoveWiresSpec extends FirrtlFlatSpec {
     // Check declaration before use is maintained
     passes.CheckHighForm.execute(result)
   }
+
+  it should "order registers respecting initializations" in {
+    val result = compileBody(
+      s"""|input clock : Clock
+          |input foo : UInt<2>
+          |output bar : UInt<2>
+          |wire y_fault : UInt<2>
+          |reg y : UInt<2>, clock with :
+          |  reset => (UInt<1>("h0"), y_fault)
+          |y_fault <= foo
+          |bar <= y
+          |""".stripMargin)
+    // Check declaration before use is maintained
+    passes.CheckHighForm.execute(result)
+  }
+
 }
-- 
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