From 082bc994457cc5f6780b58fb914a6ab3eb8a021f Mon Sep 17 00:00:00 2001
From: Albert Magyar
Date: Thu, 12 Sep 2019 17:06:01 -0700
Subject: Implement read-first memories in VerilogMemDelays

* Corrects behavior under write collisions
* Avoids heavily refactoring pass
---
 .../scala/firrtlTests/VerilogMemDelaySpec.scala    | 49 ++++++++++++++++++++++
 1 file changed, 49 insertions(+)

(limited to 'src/test')

diff --git a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
index 405f5ab5..e7f27d0e 100644
--- a/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
+++ b/src/test/scala/firrtlTests/VerilogMemDelaySpec.scala
@@ -49,4 +49,53 @@ class VerilogMemDelaySpec extends FreeSpec with Matchers {
     CheckHighForm.run(result2)
     //result.circuit.serialize.length > 0 should be (true)
   }
+
+  "Using a read-first memory should be allowed in VerilogMemDelays" in {
+    val input =
+      """
+        |circuit Test :
+        |  module Test :
+        |    input clock : Clock
+        |    input waddr : UInt<5>
+        |    input wdata : UInt<32>
+        |    input raddr : UInt<5>
+        |    input rw_wen : UInt<1>
+        |    output rdata : UInt<32>
+        |    output rw_rdata : UInt<32>
+        |    mem m :
+        |      data-type => UInt<32>
+        |      depth => 32
+        |      read-latency => 1
+        |      write-latency => 1
+        |      read-under-write => old
+        |      reader => read
+        |      writer => write
+        |      readwriter => rw
+        |    m.read.clk <= clock
+        |    m.read.en <= UInt<1>(1)
+        |    m.read.addr <= raddr
+        |    rdata <= m.read.data
+        |
+        |    m.write.clk <= clock
+        |    m.write.en <= UInt<1>(1)
+        |    m.write.mask <= UInt<1>(1)
+        |    m.write.addr <= waddr
+        |    m.write.data <= wdata
+        |
+        |    m.rw.clk <= clock
+        |    m.rw.en <= UInt<1>(1)
+        |    m.rw.wmode <= rw_wen
+        |    m.rw.wmask <= UInt<1>(1)
+        |    m.rw.addr <= waddr
+        |    m.rw.wdata <= wdata
+        |    rw_rdata <= m.rw.rdata
+      """.stripMargin
+
+    val circuit = Parser.parse(input)
+    val compiler = new LowFirrtlCompiler
+
+    val result = compiler.compile(CircuitState(circuit, ChirrtlForm), Seq.empty)
+    val result2 = VerilogMemDelays.run(result.circuit)
+    CheckHighForm.run(result2)
+  }
 }
-- 
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