From 1dcf9907eaa2f5fd2bc1e5a7dafeb1ae4b8e1434 Mon Sep 17 00:00:00 2001
From: Chick Markley
Date: Thu, 26 Jul 2018 11:18:46 -0700
Subject: Support for load memory annotations in chisel (#833)

* Support for load memory annotations in chisel
This PR
 * Delays the BlackBoxSourceHelper transformation to the Emitter stage of the VerilogCompiler
   * remove from VerilogCompiler
   * move to VerilogEmitter
 * Changes the verilog emitter to allow programmatic access to the verilog module declaration
   * Creating a bindable module requires headers to match
 * Provides a unit test that shows how to generate a bindable module.

* Binding support
Treadle needed LoadMemoryAnnotation to be in firrtl instead of chisel in order to recognize the annotations and use them for memory loading

* Binding support
- Fixed bug that handled suffixes on memory initializing files

* Binding support
- Add a bit more doc to the API provided by the VerilogRenderer
---
 src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala')

diff --git a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
index d102378f..455ceb3f 100644
--- a/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
+++ b/src/test/scala/firrtlTests/transforms/BlacklBoxSourceHelperSpec.scala
@@ -4,7 +4,7 @@ package firrtlTests.transforms
 
 import firrtl.annotations.{Annotation, CircuitName, ModuleName}
 import firrtl.transforms._
-import firrtl.{FIRRTLException, Transform, VerilogCompiler}
+import firrtl.{FIRRTLException, Transform, VerilogCompiler, VerilogEmitter}
 import firrtlTests.{HighTransformSpec, LowTransformSpec}
 import org.scalacheck.Test.Failed
 import org.scalatest.{FreeSpec, Matchers, Succeeded}
@@ -63,7 +63,7 @@ class BlacklBoxSourceHelperTransformSpec extends LowTransformSpec {
   }
 
   "verilog compiler" should "have BlackBoxSourceHelper transform" in {
-    val verilogCompiler = new VerilogCompiler
+    val verilogCompiler = new VerilogEmitter
     verilogCompiler.transforms.map { x => x.getClass } should contain (classOf[BlackBoxSourceHelper])
   }
 }
-- 
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