From cfb3a48986500422cbf6ba8887030dee3a973933 Mon Sep 17 00:00:00 2001
From: Jim Lawson
Date: Thu, 8 Dec 2016 09:25:42 -0800
Subject: Clk2clock - rename the implicit "clk" module input "clock" (#387)

* Rename implict module "clk" input to "clock".
This doesn't rename all the "self-contained" test instances.
nor the memory "clk" enables,
nor the implict module "clk"s in the regress .fir files.

* Consistency: rename implict module "clk" input to "clock" in "self-contained" test instances.
This doesn't rename the memory "clk" enables, nor the implict module "clk"s in the regress .fir files.
---
 src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala | 4 ++--
 src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala    | 2 +-
 2 files changed, 3 insertions(+), 3 deletions(-)

(limited to 'src/test/scala/firrtlTests/fixed')

diff --git a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
index 9b35a19a..2750ee71 100644
--- a/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/FixedTypeInferenceSpec.scala
@@ -264,7 +264,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : Fixed<6><<0>>
         |    output io_out : Fixed<6><<0>>
@@ -277,7 +277,7 @@ class FixedTypeInferenceSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : SInt<6>
         |    output io_out : SInt<6>
diff --git a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
index 6bd06f10..4910cb5e 100644
--- a/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
+++ b/src/test/scala/firrtlTests/fixed/RemoveFixedTypeSpec.scala
@@ -167,7 +167,7 @@ class RemoveFixedTypeSpec extends FirrtlFlatSpec {
       """
         |circuit Unit :
         |  module Unit :
-        |    input clk : Clock
+        |    input clock : Clock
         |    input reset : UInt<1>
         |    input io_in : Fixed<6><<0>>
         |    output io_out : Fixed
-- 
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